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UM027 FC6301 User Manual
4.9 FPGA device configuration
4.9.1 Flash storage
The FPGA firmware is stored on board in a flash device. The 512Mbit device is partly
used to store the configuration for both FPGAs. In the default CPLD firmware
configuration, the Virtex-6 device is directly configured from flash if a valid bitstream is
stored in the flash. The flash is pre-programmed in factory with the default firmware
example.
S29GL512M
512Mbit Flash
JTAG
CoolRunner-II
CPLD
XC2C256 VQ100
DIP switch
LED x4
Figure 6 : Configuration circuit
4.9.2 CPLD device
As shown on Figure 4, a CPLD is present on board to interface between the flash device and
the FPGA device. It is of type CoolRunner-II. The CPLD is used to program and read the
flash. The data stored in the flash is transferred from the host motherboard via the PCI bus to
the Virtex-6 device and then to the CPLD that writes the required bit stream to the storage
device. A 50MHz clock connects to the CPLD and is used to generate the configuration clock
sent to the FPGA device. At power up, if the CPLD detects that an FPGA configuration
bitstream is stored in the flash, it will start programming the FPGA device in SelectMap
mode.
The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from
a host computer via the JTAG connector. The FPGA device configuration can also be
performed using the JTAG chain.
4.9.3 DIP Switch
A switch is located next to the JTAG programming connector. The switch positions are
defined as follows:
Sw1
OFF
Default setting. The Virtex-6 configuration is loaded from the flash at power up.
ON
The Virtex-6 safety configuration is loaded from flash at power up. To be used
only if the Virtex-6 cannot be configured from flash or does not perform properly
with the switch in the OFF position.
Sw2
Reserved
Sw3
Reserved
Sw4
Reserved
Table 13: Switch description
UM027
JTAG Header
JTAG
Virtex-6
8-bit parallel
configuration
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