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UM027 FC6301 User Manual
4.2 cPCI P0 connector
A one lane PCI express is connected to a bridge device (PI7C9X110) thus making the Virtex-
6 FPGA available for access on the parallel PCI bus. The following performances have been
recorded on the bus.
PCI 33 MHz: Host to FC6301 60 Mbytes/s sustained
PCI 33 MHz: FC6301 to Host 110 Mbytes/s sustained
PCI 66 MHz: Host to FC6301 120 Mbytes/s sustained
PCI 66 MHz: FC6301 to Host 140 Mbytes/s sustained
Virtex6
Figure 3 : PCI interface diagram
4.3 Front panel IO
The FC6301 offers different front panel IO options. Not all can be used simultaneously. In
case an FMC is used no Ethernet connection is possible.
4.3.1 Gigabit Ethernet
Two Ethernet ports (RJ45 connectors) are available on the FC6301 in the front panel I/O
area. The FPGA is connected to a 2-port Ethernet PHY (88E1121) that connects to two RJ45
connectors.
The Gigabit Ethernet ports are capable to adapt to lower Ethernet speeds (10/100) if
required. This is a specific option which is not available in combination with an FMC daughter
card.
4.3.2 UART
One UART connection will be available on the fontanel via a mini USB connection. The serial
interface is made using a USB to UART Bridge (CP2102). The UART will connect directly to
the Virtex 6 FPGA via a level translator.
4.3.3 LED
Four LEDs are connected to the CPLD and are available in the front panel I/O area
UM027
32 bits PCI
33 or 66 MHz
PI7C9X110
www.4dsp.com
cPCI-P1
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r1.3
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