Fmc Gtx Reference Clock; Fmc Clock Connections - 4DSP FC6301 User Manual

UM027 FC6301 User Manual
MGT
FMC ref CLK
Virtex-6
VITA 57.1
FMC
Clock
synthesizer
CDCEL925
16 MHz
crystal
Figure 5 : Clock tree

4.8.1 FMC GTX Reference Clock

The FMC standard defines two high precision reference clocks that are driven from the FMC
to the carrier. The FC6301 connects these clocks directly to GTX reference clock inputs. The
following table shows which GTX/GTHs can use these reference clocks.
FPGA Pin
AK7
AK8
AD7
AD8

4.8.2 FMC Clock connections

The FMC clocks are connected to LVDS capable I/O on the FPGA. CLK0 and CLK1 are
connected to global clock inputs. CLK2 and CLK3 are connected to regular I/O.
FPGA Pin
AN13
AN14
AY13
AY14
AM12
AM13
AW16
AV16
UM027
FPGA
MGT
Jitter
PCIe-PCI
attenuator
and buffer
100MHz
Low jitter
LVDS
Net name
GBTCLK0_M2C_n
GBTCLK0_M2C_p
GBTCLK1_M2C_n
GBTCLK1_M2C_p
Table 11: FMC GTX reference clock connections
Net Name
CLK0_M2C_n
CLK0_M2C_p
CLK1_M2C_n
CLK1_M2C_p
CLK2_BIDIR_n
CLK2_BIDIR_p
CLK3_BIDIR_n
CLK3_BIDIR_p
Table 12: FMC clock connections
www.4dsp.com
50MHz
CDCV304
crystal
CPLD
bridge
cPCI clock
33/66 MHz
GTX REFCLK
GTXREFCLK0_112
GTXREFCLK1_113
FMC HPC
Pin Number
H5
H4
G3
G2
K5
K4
J3
J2
-
GTX/GTHs reached
112, 113
112, 113,114
Pin Name
CLK0_M2C_N
CLK0_M2C_P
CLK1_M2C_N
CLK1_M2C_P
CLK2_BIDIR_N
CLK2_BIDIR_P
CLK3_BIDIR_N
CLK3_BIDIR_P
r1.3
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