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Summary of Contents for 4DSP FC6301
- Page 1 FC6301 User Manual 4DSP LLC, USA Email: support@4dsp.com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC © 4DSP LLC 2013 UM027 www.4dsp.com...
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Page 2: Revision History
UM027 FC6301 User Manual r1.3 Revision History Date Revision Revision 2010-10-05 Draft 2010-11-21 Release 2013-04-08 Added the FMC pinout tables 2013-05-01 Updated Table 5: FMC GTX/GTH connections to use the MGTx_abc notation. Also fixed wrong reference to MGT bank 115 and changed it to MGT bank 113 Added “Table 2: P2 connections”... -
Page 3: Table Of Contents
UM027 FC6301 User Manual r1.3 Table of Contents Acronyms and related documents ................5 Acronyms ........................ 5 Related Documents ....................6 General description ..................... 6 Installation ........................8 Requirements and handling instructions ..............8 Firmware and Software ................... 8 Hardware Specification ....................8 Phycisal specifications .................... - Page 4 UM027 FC6301 User Manual r1.3 Appendix A: Errata ......................27 UM027 www.4dsp.com - 4 -...
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Page 5: Acronyms And Related Documents
UM027 FC6301 User Manual r1.3 1 Acronyms and related documents 1.1 Acronyms Analog to Digital Converter BLAST Board Level Advanced Scalable Technology CPLD Complex Programmable Logic Device Digital to Analog Converter Digitally Controlled Impedance Double Data Rate Digital Signal Processing... -
Page 6: Related Documents
FPGA algorithms for Digital Signal Processing (DSP) applications. The FC6301 product is in the 3U cPCI form factor, offering various direct on- board interface options that are closely coupled to large - fast on-board memory resources of the Xilinx Virtex™-6 FPGA. - Page 7 UM027 FC6301 User Manual r1.3 Optional Optional Gigabit VITA 57 optional Ethernet 2x Mini USB (UART) Virtex-6 128Mbit SPI flash BLAST XC6VLX240T BLAST XC6VLX365T XC6VLX550T BLAST XC6VSX315T XC6VSX475T BLAST 512Mbit CPLD parallel flash CPLD LED x4 JTAG PCIe x1 PCIe x1 to...
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Page 8: Installation
Drivers, API libraries and a program example working in combination with a pre-programmed firmware for the FPGA is provided. The FC6301 is delivered with an interface to the Xilinx PCIexpress endpoint in the Virtex-6 device and an example VHDL design so users can start performing data transfers over the PCI bus right out of the box. - Page 9 UM027 FC6301 User Manual r1.3 4.1.2 P2 connections FPGA Pin P2 pin # Signal name Bank Voltage Notes Not available on LX240T AT26 FP_RTM_0 1.8V AU27 FP_RTM_1 1.8V Not available on LX240T AK23 FP_RTM_10 1.8V Not available on LX240T BB26 FP_RTM_11 1.8V...
- Page 10 UM027 FC6301 User Manual r1.3 FP_RTM_44 1.8V Not available on LX240T FP_RTM_45 1.8V Not available on LX240T FP_RTM_46 1.8V Not available on LX240T FP_RTM_47 1.8V Not available on LX240T FP_RTM_48 1.8V Not available on LX240T FP_RTM_49 1.8V Not available on LX240T...
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Page 11: Cpci P0 Connector
Virtex6 Figure 3 : PCI interface diagram 4.3 Front panel IO The FC6301 offers different front panel IO options. Not all can be used simultaneously. In case an FMC is used no Ethernet connection is possible. 4.3.1 Gigabit Ethernet Two Ethernet ports (RJ45 connectors) are available on the FC6301 in the front panel I/O area. -
Page 12: Fpga Mezzanine Card (Fmc)
The FC6301 also connects all ten high speed differential signals (DP_M2C[9..0] and DP_C2M[9..0]). The FMC site provides flexibility for adding analog and/or digital IO via customer developed, third party or 4DSP FMC boards. 4DSP offers a wide variety of FMC cards that can be used on the FC6301: http://www.4dsp.com/fmc.php 4.4.1 Bank A (LA, HA) connections... - Page 13 UM027 FC6301 User Manual r1.3 LA_N14 LA14_N LA_P14 LA14_P LA_N15 LA15_N AA35 LA_P15 LA15_P AA30 LA_N16 LA16_N LA_P16 LA16_P AB31 LA_N17_CC LA17_N_CC AA31 LA_P17_CC LA17_P_CC LA_N18_CC LA18_N_CC LA_P18_CC LA18_P_CC LA_N19 LA19_N LA_P19 LA19_P LA_N20 LA20_N LA_P20 LA20_P LA_N21 LA21_N LA_P21...
- Page 14 UM027 FC6301 User Manual r1.3 FMC HPC FPGA Pin Net Name Pin Number Pin Name AE32 HA_N00_CC HA00_N_CC AD32 HA_P00_CC HA00_P_CC AJ35 HA_N01_CC HA01_N_CC AH34 HA_P01_CC HA01_P_CC AM42 HA_N02 HA02_N AL42 HA_P02 HA02_P AM41 HA_N03 HA03_N AL41 HA_P03 HA03_P AL40...
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Page 15: Bank B (Hb) Connections
UM027 FC6301 User Manual r1.3 AB36 HA_N19 HA19_N AC36 HA_P19 HA19_P AB33 HA_N20 HA20_N AB32 HA_P20 HA20_P AB42 HA_N21 HA21_N AA42 HA_P21 HA21_P AB41 HA_N22 HA22_N AA41 HA_P22 HA22_P AA40 HA_N23 HA23_N AB39 HA_P23 HA23_P Table 4: FMC HA connections 4.4.2 Bank B (HB) connections... -
Page 16: Gigabit Transceiver Connections
HB21_P Table 5: FMC HB connections 4.4.3 Gigabit transceiver connections The FC6301 connects the ten DP signals on the FMC connector to gigabit transceivers (GTX blocks) on the FPGA. The reference clock connections are described in section 4.8.1. FMC HPC... -
Page 17: Miscellaneous Fmc Connections
UM027 FC6301 User Manual r1.3 DP_C2M_P3 DP3_C2M_P DP_M2C_N3 DP3_M2C_N DP_M2C_P3 DP3_M2C_P DP_C2M_N4 MGT3_113 DP4_C2M_N DP_C2M_P4 DP4_C2M_P DP_M2C_N4 DP4_M2C_N DP_M2C_P4 DP4_M2C_P DP_C2M_N5 MGT1_114 DP5_C2M_N DP_C2M_P5 DP5_C2M_P DP_M2C_N5 DP5_M2C_N DP_M2C_P5 DP5_M2C_P DP_C2M_N6 MGT0_114 DP6_C2M_N DP_C2M_P6 DP6_C2M_P DP_M2C_N6 DP6_M2C_N DP_M2C_P6 DP6_M2C_P DP_C2M_N7 MGT2_113... -
Page 18: Spi Flash
(SN74AVC4T245). 4.6 Virtex-6 FPGA device The Virtex-6 FPGA device is the DSP processing node of the FC6301. The Virtex-6 FPGA device is from the Virtex-6 SXT and LXT family in a 1759 balls fine line ball grid array package. It can be an XC5VLX240T, XC5VLX365T, XC5VLX550T, XC5VSX315T or XC5VSX475T. -
Page 19: Blast Sites
Table 10: BLAST Memory/Processing Options 4.8 Clock tree The FC6301 clock architecture offers an efficient distribution of low jitter clocks. A 100 MHz clock from a low jitter oscillator is distributed to the FPGA and the PCIexpress to PCI bridge using a PCI express jitter attenuator (ICS847003). -
Page 20: Fmc Gtx Reference Clock
The FMC standard defines two high precision reference clocks that are driven from the FMC to the carrier. The FC6301 connects these clocks directly to GTX reference clock inputs. The following table shows which GTX/GTHs can use these reference clocks. -
Page 21: Fpga Device Configuration
UM027 FC6301 User Manual r1.3 4.9 FPGA device configuration 4.9.1 Flash storage The FPGA firmware is stored on board in a flash device. The 512Mbit device is partly used to store the configuration for both FPGAs. In the default CPLD firmware configuration, the Virtex-6 device is directly configured from flash if a valid bitstream is stored in the flash. -
Page 22: Cpld Leds And Board Status
Table 14: LED board status 4.9.5 JTAG A JTAG connector footprint is available on the FC6301 for configuration purposes and the JTAG chain can be accessed using a press-fit JTAG connector. The JTAG chain is connected via a DIP switch that enables the following configurations: ... -
Page 23: Power Supply
UM027 FC6301 User Manual r1.3 4.10 Power supply The Power is supplied to the FC6301 via the CompactPCI connectors. Several DC-DC converters generate the appropriate voltage rails for the different devices and interfaces present on board. The FC6301 power distribution is as follows:... -
Page 24: Hotswap
UM027 FC6301 User Manual r1.3 Table 15 : Power supply 4.11 Hotswap Hot Swap is the act of removal and insertion of cards into a platform while that system is operational. This process should not cause any failures on the systems power supply and system’s I/O signals. - Page 25 UM027 FC6301 User Manual r1.3 Parameter: Device 2 Formula On-chip temperature ADT7411 Die Temperature On-chip AIN0 (V +3.3V External AIN1 BLAST0_vcore AIN1 External AIN2 BLAST2_vcore AIN2 External AIN3 AIN3*(1249/249) External AIN4 AIN4 External AIN5 VADJ AIN5 External AIN6 AIN6 External AIN7...
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Page 26: Environment
C to +120 5.2 Convection cooling The air flow provided by the chassis fans the FC6301 is enclosed in will dissipate the heat generated by the on board components. A minimum airflow of 300 LFM is recommended. Optionally a low profile heat sink/fan can be glued on top of the Quad ADC. The card has a fan power connection that can be switch on and off under carrier card control (TBD). - Page 27 UM027 FC6301 User Manual r1.3 Appendix A: Errata PCB revision 2.1 SPI FLASH not supported. UM027 www.4dsp.com - 27...