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UM027 FC6301 User Manual
AH40
AJ42
The I/O standard to be assigned depends on VADJ configuration, by default this is 2V5.
Contact factory for other VADJ voltages.
The FMC I2C bus signals connect to the CPLD and can be controlled from the FPGA using
two signals per I2C line. The connections and CPLD logic are depicted in the following
image.
FPGA
4.5 SPI flash
A 128 Mbits serial flash device (S25FL128P) will be available to the Virtex-6 device. This
flash allows the storage of vital data like processor boot code and settings into a non volatile
memory.
The flash is operated using a standard SPI interface that can run up to 104 MHz, allowing for
a page programming speed up to 208 KB/s. Reading data from the flash can be done at
speeds up to 13 MB/s.
The SPI programming pins will be connected to a bank that supports 1V8, whereas the serial
flash will be operating at 3V3. This will not cause problems for the signals from the Virtex-6 to
the flash device but the signal from the flash device to the Virtex-6 will pass through a level
translator (SN74AVC4T245).
4.6 Virtex-6 FPGA device
The Virtex-6 FPGA device is the DSP processing node of the FC6301. The Virtex-6 FPGA
device is from the Virtex-6 SXT and LXT family in a 1759 balls fine line ball grid array
package. It can be an XC5VLX240T, XC5VLX365T, XC5VLX550T, XC5VSX315T or
XC5VSX475T.
UM027
PRSNT_M2C_L
PG_C2M
Table 7: Miscellaneous FMC connections
SCL_oe
SCL
SDA_oe
SDA
Figure 4: FMC I2C connections
FPGA Pin
AT12
BA15
BA14
AR12
Table 8: FMC I2Cconnections
www.4dsp.com
I
H2
O
D1
CPLD
0
0
Net Name
DIR
SCL_oe
SCL
SDA_oe
SDA
-
PRSNT_M2C_L
PG_C2M
FMC
SCL
SDA
O
I
O
I
r1.3
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