Fpga Mezzanine Card (Fmc); Bank A (La, Ha) Connections - 4DSP FC6301 User Manual

UM027 FC6301 User Manual

4.4 FPGA Mezzanine Card (FMC)

The Virtex-6 FPGA interfaces to an FPGA Mezzanine Card (FMC) via a high pin count (HPC)
VITA 57.1 site. All the differential and control signals are connected to the Virtex-6 FPGA.
The FC6301 also connects all ten high speed differential signals (DP_M2C[9..0] and
DP_C2M[9..0]).
The FMC site provides flexibility for adding analog and/or digital IO via customer developed,
third party or 4DSP FMC boards. 4DSP offers a wide variety of FMC cards that can be used
on the FC6301: http://www.4dsp.com/fmc.php

4.4.1 Bank A (LA, HA) connections

Differential routing is applied with matched delay within pairs on bank A (LA, HA).
FPGA Pin
AF30
AE30
AK37
AJ37
AK30
AJ31
AJ32
AK33
AG29
AH29
AG39
AF39
AG37
AF37
AG33
AF32
AF41
AF42
AE42
AD42
AD38
AE38
AD30
AD31
Y39
Y40
AA39
Y38
UM027
Net Name
LA_N00_CC
LA_P00_CC
LA_N01_CC
LA_P01_CC
LA_N02
LA_P02
LA_N03
LA_P03
LA_N04
LA_P04
LA_N05
LA_P05
LA_N06
LA_P06
LA_N07
LA_P07
LA_N08
LA_P08
LA_N09
LA_P09
LA_N10
LA_P10
LA_N11
LA_P11
LA_N12
LA_P12
LA_N13
LA_P13
www.4dsp.com
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FMC HPC
Pin Number Pin Name
G7 LA00_N_CC
G6 LA00_P_CC
D9 LA01_N_CC
D8 LA01_P_CC
H8 LA02_N
H7 LA02_P
G10 LA03_N
G9 LA03_P
H11 LA04_N
H10 LA04_P
D12 LA05_N
D11 LA05_P
C11 LA06_N
C10 LA06_P
H14 LA07_N
H13 LA07_P
G13 LA08_N
G12 LA08_P
D15 LA09_N
D14 LA09_P
C15 LA10_N
C14 LA10_P
H17 LA11_N
H16 LA11_P
G16 LA12_N
G15 LA12_P
D18 LA13_N
D17 LA13_P
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