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UX-A1000U
Hurricane (IC1) Terminal descriptions
Pin
Block
Pin Name
No.
FLASH
129
D8
INTERFACE 132
D9
134
D10
137
D11
140
D12
146
D13
149
D14
152
D15
DRAM
170
DRAM_nRAS
174
DRAM_nLCAS
172
DRAM_nUCAS
175
DRAM_nWE
177
DRAM_nOE
195
DRAM_A0
196
DRAM_A1
199
DRAM_A2
200
DRAM_A3
190
DRAM_A4
188
DRAM_A5
187
DRAM_A6
185
DRAM_A7
183
DRAM_A8
178
DRAM_A9
144
DRAM_D00 I/O
147
DRAM_D01 I/O
151
DRAM_D02 I/O
153
DRAM_D03 I/O
163
DRAM_D04 I/O
165
DRAM_D05 I/O
166
DRAM_D06 I/O
169
DRAM_D07 I/O
158
DRAM_D08 I/O
157
DRAM_D09 I/O
156
DRAM_D10 I/O
155
DRAM_D11 I/O
143
DRAM_D12 I/O
141
DRAM_D13 I/O
139
DRAM_D14 I/O
138
DRAM_D15 I/O
ARM
164
ARM_nRW
171
ARM_BL0
173
ARM_BL1
176
ARM_BL2
179
ARM_BL3
181
ARM_MAS0
184
ARM_MAS1
186
ARM_MClk
189
ARM_nM0
192
ARM_nM1
I/O
Pin Description
I/O
Data 08
I/O
Data 09
I/O
Data 10
I/O
Data 11
I/O
Data 12
I/O
Data 13
I/O
Data 14
I/O
Data 15
O
DRAM Row Address Strobe
O
DRAM Lower Column
Address Strobe
O
DRAM Upper Column
Address Strobe
O
DRAM Write Enable
O
DRAM Output Enable
O
DRAM Address 0
O
DRAM Address 1
O
DRAM Address 2
O
DRAM Address 3
O
DRAM Address 4
O
DRAM Address 5
O
DRAM Address 6
O
DRAM Address 7
O
DRAM Address 8
O
DRAM Address 9
DRAM Data 00
DRAM Data 01
DRAM Data 02
DRAM Data 03
DRAM Data 04
DRAM Data 05
DRAM Data 06
DRAM Data 07
DRAM Data 08
DRAM Data 09
DRAM Data 10
DRAM Data 11
DRAM Data 12
DRAM Data 13
DRAM Data 14
DRAM Data 15
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
5 – 17
Pin
Block
Pin Name
No.
194
ARM_nM2
197
ARM_nM3
198
ARM_nM4
201
ARM_nMREQ
204
ARM_nOPC
206
ARM_nWait
RESET
40
nRESET
WATCHDOG 73
WATCHDOG
TEST PIN
29
Test1
35
Test2
37
Test3
Hurricane BLOCK DIAGRAM
CLK_IN
SSCG
OSC
BLOCK
CLK_OUT
48MHz
SNR_CHA
SNR_CHB
I/O
BLOCK
PIN
SN_COVER
USB_HIGH
USB_CON
USB
D+
PORT
D–
C(0:7)
–SLCTIN
–INIT
–STROBE
1284
PARALLEL
PARALLEL
BUSY
PORT
PERROR
SLCT
–ACK
DRAM
I/F
I/O
Pin Description
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
O
Not use
I
RESET
O
WATCHDOG
I
TEST PIN
I
TEST PIN
I
TEST PIN
+3.3V
+2.5V
VDD/VSS
GROUND
CPU CORE
ARM7TDMI
CONTROL(1:8)
DATA(0:3)
PRINTHEAD
ASIC
ACLK
INTERFACE
PCLK
–CS
SCK
ANALOG
ASIC
SDI
INTERFACE
USB
DCM_PWM
CORE
–RESET
RESET
TEST
TEST
–CE
–OE
USER
FLASH
D(0:15)
LOGIC
ROM-I/F
A(0:23)
–WE
TCLK
TMODSEL
TDIN
JTAG
TDOUT
PORT
–TRESET
Fig. 9
PRINTHEAD
DRIVER
ASIC
ANALOG
ASIC
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