Appendix A Register Structure And Format - Advantech PCL-740 User Manual

BASE+1 Interrupt Status Register (ISR) when DLAB=0
bit 0 Enable received-data-available interrupt
bit 1 Enable transmitter-holding-register-empty
bit 2 Enable receiver-line-status interrupt
bit 3 Enable modem-status interrupt
BASE+2 FIFO Control Register (FCR)
bit 0 Enable transmit and receive FIFOs
bit 1 Clear contents of receive FIFO
bit 2 Clear contents of transmit FIFO
bits 6-7 Set trigger level for receiver FIFO interrupt.
Bit 7
0
0
1
1
BASE+3 Line Control Register (LCR)
bit 0 Word length select bit 0
bit 1 Word length select bit 1
Bit 1
0
0
1
1
bit 2 Number of stop bits
bit 3 Parity enable
bit 4 Even parity select
bit 5 Stick parity
bit 6 Set break
bit 7 Divisor Latch Access Bit (DLAB)
interrupt
Bit 6 FIFO trigger level
0 01
1 04
0 08
1 14
Bit 0 Word length (bits)
0 5
1 6
0 7
1 8

Appendix A Register structure and format

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