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BIOS Setup
Frequency Control
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency. Settings:
,
and
.
By SPD
100MHz
133MHz
DRAM Timing
This setting determines whether DRAM timing is configured by reading the
contents of the SPD (Serial Presence Detect) EPROM on the DRAM
module. Selecting
makes SDRAM CAS Latency and Bank Interleave
By SPD
automatically determined by BIOS according to the configurations on the
SPD. Settings:
and
.
Manual
By SPD
SDRAM CAS Latency
Set the time between SDRAM read command and when the data actually
becomes available. Settings:
and
.
2
2.5
Bank Interleave
Set the interleave mode of the SDRAM interface. Interleaving allows banks
of SDRAM to alternate their refresh and access cycles. One bank will
undergo its refresh cycle while another is being accessed. This improves per-
formance of the SDRAM by masking the refresh time of each bank. Settings:
,
and
.
Disabled
2 Bank
4 Bank
3-27
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