Integra DTR-5.9 Service Manual page 80

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-43
Q8501 : SiI9135ACTU ( HDMI Receiver)-5/5
TERMINAL DESCRIPTION
Differential Signal Data Pins
Pin Name Pin #
R0XC+ 40
R0XC- 39
R0X0+ 44
R0X0- 43
R0X1+ 48
R0X1- 47
R0X2+ 52
R0X2- 51
R1XC+ 58
R1XC- 57
R1X0+ 62
R1X0- 61
R1X1+ 66
R1X1- 65
R1X2+ 70
R1X2- 69
Power and Ground Pins
Pin Name Pin #
TE
L 13942296513
CVCC18 12, 24, 25, 80, 91, 107, 119, 131, 143
CGND 11, 23, 79, 90, 106, 118, 130, 142
IOVCC33 6, 18, 32, 74, 88, 104, 113, 125, 137
IOGND 4, 17, 31, 73, 87, 103, 112, 124, 136
AVCC33 38, 42, 46, 50, 56, 60, 64, 68
AGND 36, 41, 45, 49, 53, 59, 63, 67, 71
AVCC18 37, 54, 72
DVCC18 92
DGND 93
XTALVCC 96
REGVCC 97
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Dir Description
Input TMDS Input Clock Pair
Input
Input TMDS Input Data Pair
Input
Input TMDS Input Data Pair
Input
Input TMDS Input Data Pair
Input
Input TMDS Input Clock Pair
Input
Input TMDS Input Data Pair
Input
Input TMDS Input Data Pair
Input
Input TMDS Input Data Pair
Input
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8
HDMI Port 0
HDMI Port 1
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Type Description
3 6 7 1 3 1 5
Power Digital Logic VCC.
Ground Digital Logic GND.
Power Input/Output Pin VCC.
Ground Input/Output Pin GND.
Power TMDS Analog VCC 3.3V.
Ground TMDS Analog GND.
Power TMDS Analog VCC 1.8V.
Power Audio Clock Regeneration PLL.
Analog VCC. Must be connected to 1.8V.
Ground Audio Clock Regeneration PLL.
Analog Ground.
Power Audio Clock Regeneration PLL
Crystal Oscillator Power. Must be connected to 3.3V.
Power Audio Clock Regeneration PLL.
Crystal Regulator Power. Must be connected to 3.3V.
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9 4 2 8
0 5 8 2 9 9 4 2 8
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DTR-5.9
9 9
9 9