Integra DTR-5.9 Service Manual page 43

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-6
Q281 : M12L64164A-7TG ( 1M x 16 Bit x 4 Banks Synchronous DRAM )
BLOCK DIAGRAM
CLK
Clock
Generator
CKE
Address
CS
RAS
CAS
WE
TE
L 13942296513
TERMINAL DESCRIPTION
Pin Name
CLK
CS
CKE
A0 ~ A11
A12 , A13
RAS
CAS
WE
L(U)DQM
DQ0 ~ DQ15
VDD / VSS
www
VDDQ / VSSQ
NC
.
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Row
Address
Buffer
&
Mode
Refresh
Register
Counter
Column
Address
Buffer
&
Refresh
Counter
Data Control Circuit
Description
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7.
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with CAS low. Enables column access.
Enables write operation and row precharge. Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t after the clock and masks the output.
SHZ
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
This pin is recommended to be left No Connection on the device.
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8
Bank D
Bank C
Bank B
Bank A
L(U)DQM
Sense Amplifier
Column Decoder
Q Q
3 6 7 1 3
u163
.
2 9 9 4 2 8
PIN LAYOUT
TOP VIEW
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
VDD 14
LDQM 15
WE 16
CAS 17
RAS 18
CS 19
A13 20
A12 21
DQ
A10/AP 22
A0 23
A1 24
A2 25
A3 26
VDD 27
1 5 0 5 8 2 9 9 4
m
co
DTR-5.9
9 9
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
2 8 9 9