Integra DTR-5.9 Service Manual page 76

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-39
Q8501 : SiI9135ACTU ( HDMI Receiver)-1/5
BLOCK DIAGRAM
DSDA0
Port
DSCL0
MUX
DSDA1
DSCL1
R1XC
TMDS
R1X0
Digital
Core
R1X1
R1X2
TE
L 13942296513
R0XC
TMDS
R0X0
Digital
Core
R0X1
R0X2
R0PWR5V
R1PWR5V
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http://www.xiaoyu163.com
2
I C
Slave
HDCP
Embedded
Keys
24-Bit
Data
HDCP &
HS, VS,
Repeater
DE
Decryption
Engine
Port
MUX
24/30/36-Bit
Encrypted Pixel
Data
HS, VS,
DE
36-Bit
Data
Detect
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2 9
8
Registers
Configuration
Logic Block
Q Q
3 6 7 1 3
XOR
Mask
24/30/36-Bit
Decrypted Pixel
Data
Control Signals
Video
Deep Color
Space
Converter
Up/Down
Sampling
Port
co
.
9 4 2 8
2
I C
Slave
Aux
MCLK
Data
Gen
HDMI
Mode
Audio
Control
Data
1 5 0 5 8 2 9 9 4
Decode
36
Auto A/V
Exception
Handling
m
DTR-5.9
9 9
RESET#
INT
CSDA
CSCL
MCLKOUT
XTALIN
XTALOUT
SCK
WS
SD[3:0]
SPDIF
2 8 9 9
DCLK
DL[3:0]
DR[3:0]
EVNODD
DE
HSYNC
VSYNC
ODCK
Q[35:0]
MUTEOUT
SCDT