Integra DTR-5.9 Service Manual page 74

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-37
Q8401 : SiI9134CTU (HDMI Deep Color Transmitter)-3/4
TERMINAL DESCRIPTION
Video and Audio Input pins
Pin Name
D0 - D11
D12 - D23
D24 - D35
Video and Audio Input pins
Pin Name
IDCK
DE
HSYNC
VSYNC
SCK
WS
SD0
SD1
SD2
SD3
DL0
TE
DR0
L 13942296513
DL1
DR1
DL2
DR2
DL3
DR3
DCLK
MCLK
SPDIF
Configuration / Programming Pins
Pin Name
HPD
RSVDL
INT
Control Pins
Pin Name
CI2CA
RESET#
CSCL
www
CSDA
DSCL
DSDA
.
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Pin # Dir Description
98 - 84 Input These are the lower 12 bits of the 36-bit pixel bus.
These pins are highly configurable, and support multiple RGB and YCbCr formats.
83 - 71 Input These are the middle 12 bits of the 36-bit pixel bus.
70 - 56 Input These are the upper 12 bits of the 36-bit pixel bus.
Pin # Dir Description
88 Input Input Data clock
1 Input Data enable
2 Input Horizontal Sync input control signal
3 Input Vertical Sync input control signal
2
11 Input I S Serial Clock
2
10 Input I S Word Select
2
9 Input I S Serial data
2
8 Input I S Serial data
2
7 Input I S Serial data
2
6 Input I S Serial data
17 Input One-bit Audio data Left 0
16 Input One-bit Audio data Right 0
19 Input One-bit Audio data Left 1
18 Input One-bit Audio data Right 1
21 Input One-bit Audio data Left 2
20 Input One-bit Audio data Right 2
23 Input One-bit Audio data Left 3
22 Input One-bit Audio data Right 3
15 Input One-bit Audio Clock Input
5 Input Audio Input Master Clock
4 Input S/PDIF Audio Input.
Pin # Dir Description
51 Input Hot Plug Detect Input.
52 Input Reserved for use by Silicon Image and must be tied LOW.
24 Output Interrupt Output.
Pin # Dir Description
2
50 Input I C device address select
25 Input Reset Pin (Active LOW) 5V Tolerant
2
48 Input I C Clock
2
49 Bi-Di I C Data (Open Drain Output)
46 Bi-Di DDC Clock (Open Drain Output)
x ao
y
47 Bi-Di DDC Data (Open Drain Output)
i
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