Pioneer DJM-900NXS Service Manual page 182

1
A
G
MAIN ASSY
DIR_ADC_DAC_RESET
1-28
V: 1.0 V/div. H: 1 mS/div.
B
DIT_RST
1-29
V: 1.0 V/div. H: 1 mS/div.
C
FPGA_RST
1-30
V: 1.0 V/div. H: 1 mS/div.
D
24M_CLK_USB
1-35
V: 1.0 V/div. H: 10 nS/div.
E
USB_RESET
1-36
V: 1.0 V/div. H: 1 mS/div.
F
182
1
2
CPU_MUTE
1-38
V: 1.0 V/div. H: 1 mS/div.
CPU_RESET
1-39
V: 1.0 V/div. H: 1 mS/div.
20M_CLK_MAIN
1-40
V: 1.0 V/div. H: 20 nS/div.
20M_CLK_SH
1-41
V: 1.0 V/div. H: 20 nS/div.
24.5764_CLK
1-42
V: 1.0 V/div. H: 20 nS/div.
DJM-900NXS
2
3
SUB_SH_RST
1-43
V: 1.0 V/div. H: 1 mS/div.
96k_CLK_AIN
1-44
V: 1.0 V/div. H: 2 μS/div.
6M_CLK_AIN
1-45
V: 1.0 V/div. H: 50 nS/div.
24M_CLK_AIN
1-46
V: 1.0 V/div. H: 10 nS/div.
24M_CLK_ADDA
1-47
V: 1.0 V/div. H: 10 nS/div.
3
4
6M_CLK_ADDA
1-48
V: 1.0 V/div. H: 50 nS/div.
96k_CLK_ADDA
1-49
V: 1.0 V/div. H: 2 μ/div.
24M_CLK_FPGA
1-53
V: 1.0 V/div. H: 10 nS/div.
SH_FPGA_DONE
1-54
V: 1.0 V/div. H: 1 mS/div.
24.5M_CLK_DSP
1-59
V: 1.0 V/div. H: 10 nS/div.
4