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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-26
Q8001
: FLI30502 (LCD TV Controller with Worldwide Standard Sound Processor
and HDMI Receiver)-8/12
TERMINAL DESCRIPTION
LVDS Display interface
Pin Name
PBIAS
PPWR
AVDD_LV_33
AVSS_LV
CH3P_LV_E
CH3N_LV_E
CLKP_LV_E
CLKN_LV_E
CH2P_LV_E
CH2N_LV_E
CH1P_LV_E
CH1N_LV_E
CH0P_LV_E
CH0N_LV_E
VSS_OUT_LV
VDD_OUT_LV_33
CH3P_LV_O
CH3N_LV_O
CLKP_LV_O
CLKN_LV_O
CH2P_LV_O
CH2N_LV_O
CH1P_LV_O
CH1N_LV_O
CH0P_LV_O
CH0N_LV_O
AVSS_OUT_LV
AVDD_OUT_LV_33
Pin #
I/O
Description
71
O
Panel Bias Control (backlight enable, tri-state output, 5 V tolerant).
O
72
Panel Power Control (tri-state output, 5 V tolerant).
DP
74
Digital Power for LVDS Block. Connect to digital 3.3V supply.
G
73
Ground for LVDS outputs.
75
O
These form the Differential Data Output for Channel 3 (Even).
76
O
77
O
These form the Differential Clock Output Even Channel.
O
78
O
79
These form the Differential Data Output for Channel 2 (Even).
O
80
O
81
These form the Differential Data Output for Channel 1 (Even).
82
O
83
O
These form the Differential Data Output for Channel 0 (Even).
84
O
G
85
Ground for LVDS outputs.
DP
86
Digital Power for LVDS outputs. Connect to digital 3.3 V supply.
O
87
These form the Differential Data Output for Channel 3 (Odd).
O
88
89
O
These form the Differential Clock Output Odd Channel.
90
O
91
O
These form the Differential Data Output for Channel 2 (Odd).
O
92
O
93
These form the Differential Data Output for Channel 1 (Odd).
O
94
O
95
These form the Differential Data Output for Channel 0 (Odd).
96
O
97
G
Ground for LVDS outputs.
98
DP
Digital Power for LVDS outputs. Connect to digital 3.3 V supply.
TX-SR606
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