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LC272D0BT-WA6 (IC6) Terminal description (2/2)
PIN
I/O
Name
109
P
VSS
Ground
110
I
TEST0
Test pin 0
111
I
TEST1
Test pin 1
112
I
XINSC
Image block Clock in
113
O
XOUTSC
Image block Clock out
114
P
VSS
Ground
115
O
TOUT
Test pin
116
O
LININT
Monitor for line interval signal
117
O
SAMP
Monitor for sampling point
SH
118
O
Line shift clock (CIS)
119
O
CLK1
Transfer clock (CIS)
120
P
AVDD
Power supply (Analogue)
121
P
AVSS
Analogue Ground
122
I
ADREFL
Low reference voltage (ADC)
123
I
TEMP
Temperature detect
124
I
AVO
Video signal for scanning
125
O
ATAPH
High reference voltage (ADC)
126
P
AVDD
Power supply (Analogue)
127
P
AVSS
Analogue Ground
128
P
VDD
Power supply
129
P
VSS
Ground
130
O
PLTSW
Plate SW detect
131
O
BKLON
Back light on/off control
132
I
SEN7
Key sense signal
133
I
SEN6
Key sense signal
134
I
SEN5
Key sense signal
135
I
SEN4
Key sense signal
136
I
SEN3
Key sense signal
137
I
SEN2
Key sense signal
138
I
SEN1
Key sense signal
139
I
SEN0
Key sense signal
140
B
LD15
LED
141
B
LD14
LED
142
B
LD13
LCD drive signal
143
B
LD12
LCD drive signal
144
P
VDD
Power supply
145
P
VSS
Ground
146
B
LD11
Reserved
147
B
LD10
Reserved
148
B
LD9
Reserved
149
B
LD8
Reserved
150
B
LD7
LCD drive
151
B
LD6
LCD drive
152
B
LD5
LED/LCD drive
153
B
LD4
LED/LCD drive
154
B
LD3
Key matrix select/LED/LCD drive
155
B
LD2
Key matrix select/LED/LCD drive
156
B
LD1
Key matrix select/LED/LCD drive
157
B
LD0
Key matrix select/LED/LCD drive
158
O
TXB
Current direction (Phase B)
159
O
TXBI1
Current control 1 (Phase B)
160
O
TXBI0
Current control 0 (Phase B)
161
O
TXA
Current direction (Phase A)
162
P
VDD
Power supply
Function
PIN
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
5 – 7
I/O
Name
P
VSS
Ground
O
TXAI1
Current control 1 (Phase A)
O
TXAI0
Current control 0 (Phase A)
O
CRNT0
Current change signal 0
O
CRNT1
Current change signal 1
O
XLBE
Low byte(D7-D0) enable signal
I
XRESET
System Reset Signal
O
XMANRES
Manual Reset Signal
O
XNANDOPCS
Chip select (Optional memory)
O
XNANDSTDCS Chip select (Standard memory)
O
XNANDRD
Read signal (Nand flash)
O
XNANDWR
Write signal (Nand flash)
O
XWP0
Write protect (Standard)
Write protect (Optional)
O
XWP1
O
ALEO
Address latch enable (Flash memory)
O
CLEO
Command latch enable (Flash memory)
I
SHCK
CPU Outer bus Clock
P
VDD
Power supply
P
VSS
Ground
I
RXW
Read/Write signal
I
XBS
Bus cycle start signal
I
A25
Address bus bit25
I
A24
Address bus bit24
I
A23
Address bus bit23
I
A22
Address bus bit22
I
A21
Address bus bit21
I
A20
Address bus bit20
I
A13
Address bus bit13
I
A12
Address bus bit12
I
A11
Address bus bit11
I
A10
Address bus bit10
I
A9
Address bus bit9
I
A8
Address bus bit8
I
A7
Address bus bit7
I
A6
Address bus bit6
P
VDD
Power supply
P
VSS
Ground
I
A5
Address bus bit5
I
A4
Address bus bit4
I
A3
Address bus bit3
I
A2
Address bus bit2
I
A1
Address bus bit1
I
A0
Address bus bit0
B
XWE0
D7-D0 select signal
B
XOPDEN
Bus buffer enable control
B
D15
Data bus bit15
B
D14
Data bus bit14
B
D13
Data bus bit13
B
D12
Data bus bit12
B
D11
Data bus bit11
B
D10
Data bus bit10
B
D9
Data bus bit9
B
D8
Data bus bit8
P
VDD
Power supply
FO-4450U/FO-CS1
Function
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