Sharp FO-4450 Service Manual page 80

FO-4450U/FO-CS1
LC272D0BT-WA6 (IC6) Terminal description (1/2)
PIN I/O Name
P
1 VSS Ground
2 B D7 Data bus
3 B D6 Data bus
4 B D5 Data bus
5 B D4 Data bus
6 B D3 Data bus
7 B D2 Data bus
8 B D1 Data bus
9 B D0 Data bus
Chip select (Erea 0)
10 I XCS0
11 I XCS4 Chip select (Erea 4)
12 O XDACK0 DMA acknowledge (Ch0)
13 O XDACK1 DMA acknowledge (Ch1)
14 O XDRAK0 DMA request acknowledge (Ch0)
15 O XDRAK1 DMA request acknowledge (Ch1)
16 I XDREQ0 DMA request (Ch0)
17 I XDREQ1 DMA request (Ch1)
18 P VDD Power supply
19 P VSS Ground
20 O XFLCS Chip select (Flash memory)
21 I XFLSHINTA Interrupt request of flash memory
22 I XFLSHINTB Interrupt request of flash memory
23 O XINT0 Interrupt request signal
24 O XINT1 Interrupt request signal
25 O XINT2 Interrupt request signal
26 O XINT3 Interrupt request signal
Chip select (Program memory)
27 O XPGMCS
28 O XWROUT Write strobe signal
Read strobe signal
29 O XRDOUT
30 O XWAIT Wait request signal
31 I XBUSYDP Busy signal of Dual port RAM
Interrupt request from modem chip 1
32 I XMDMINT1
Interrupt request from modem chip 0
33 I XMDMINT0
34 O XMDMCS1 Chip select (Modem Chip 1)
35 O XMDMCS0 Chip select (Modem Chip 0)
36 P VDD Power supply
37 P VSS Ground
Print block clock in
38 I XINPRT
39 O XOUTPRT Print block clock out
40 P VSS Ground
41 I TODB Top of data
42 I HSYNC Synchronous signal of horizontal anxious
43 O PDATA Print data
44 I XJBGINT1 Reserved
45 I XJBGINT0 Reserved
46 I XSGAINT Interrupt request from modem chip 0
47 I XSBGA Chip select (Sub Gate array)
48 I JBGDREQ00 Reserved
49 I JBGDREQ01 Reserved
50 I JBGDREQ10 Reserved
51 I JBGDREQ11 Reserved
52 O XJBGACK1 Reserved
53 O XJBGACK0 Reserved
54 P VDD Power supply
Function PIN
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
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108
5 – 6
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I/O Name
P VSS Ground
O XNICACK Acknowledge signal for NIC
I XNICINT Interrupt request from NIC board
O XNICCS Chip select (NIC Board)
O XJBG1 Reserved
O XJBG0 Reserved
B MAD0 Data bus of page memory
B MAD1 Data bus of page memory
P VDD Power supply
P VSS Ground
B MAD2 Data bus of page memory
B MAD3 Data bus of page memory
B MAD4 Data bus of page memory
B MAD5 Data bus of page memory
B MAD6 Data bus of page memory
B MAD7 Data bus of page memory
B MAD8 Data bus of page memory
P VDD Power supply
P VSS Ground
B MAD9 Data bus of page memory
B MAD10 Data bus of page memory
B MAD11 Data bus of page memory
B MAD12 Data bus of page memory
B MAD13 Data bus of page memory
B MAD14 Data bus of page memory
B MAD15 Data bus of page memory
P VDD Power supply
P VSS Ground
O SDCLK Clock of page memory
O DQMUL Data mask of page memory
O CKE CK enable of page memory
O CASB CAS of page memory
O RASB RAS of page memory
DWEB Write strobe of page memory
O
O XCSDRM0 Chip select of page memory
P VDD Power supply
P VSS Ground
O MA0 Address bus of page memory
O MA1 Address bus of page memory
O MA2 Address bus of page memory
O MA3 Address bus of page memory
O
MA4 Address bu s of page memory
O MA5 Address bus of page memory
O MA6 Address bus of page memory
VDD Power supply
P
P VSS Ground
O MA7 Address bus of page memory
O MA8 Address bus of page memory
O MA9 Address bus of page memory
O MA10 Address bus of page memory
O MA11 Address bus of page memory
O MA12 Address bus of page memory
O MA13 Address bus of page memory
P VDD Power supply
Function