Block Diagram - Marantz CDR631 Service Manual

7.2 Audio Board
The Audio board for the CDR631 is a full high performance
AD/DA panel, acting as an interface to the outside world. Key
components are DS1807, ADC AK5351 and DAC AK4393.
7.2.1 Analog-in path
Description
The via BALANCE in connected anolog-in L and R signals are
pre-amplified by opamp Q761-Q763, and the via UNBALANCE
in connected anolog-in L and R signals are pre-amplified by
opamp Q705, Q706, these signals is selected by Analog SW
Q701 after which they are presented to an adjustable amplifier
made out of DS1807 and opamp Q703 - Q708. The level of the
incoming. Analog signal is adjusted by means of control lines
2
"I C" coming from the DASP on the CDR main board and
switching the mux/demux. The anolog signal is then presented
to the A/D converter A5351 (QA01) where they are converted
2
from analog to I S-bus data format. The I
via connector J601 and flex to the DASP on the CDR main
board. The ADC uses the CL11-clock (11.2896 MHz), coming
from the DASP on the CDR main board.
ADC AK5351
Description
The AK5351 is a stereo, 20-bit oversampling ADC based on
Sigma Delta technology intended primarily for digital audio
bandwith applications. It supports the I2S-bus data format. The
device can be used in either slave or master mode. In this
application it is used in slave mode receiving it's clock from the
DASP on the CDR main board.

Block diagram

AGND VA VD DGND VB
5 4 2
3
VREF
Voltage
Reference
6
AINL+ ∆ Σ
7
Modulator
AINL -
1
AINR+ ∆ Σ
2
Modulator
AINR -
2
S-bus is connected
SMODE1
CMODE MCLK SMODE2
13 24 22 17 15
Clock Divider
16 9 8
PD HPFE TST1 TST2 TST3 TST4
Figure 7-10
Pin description
No. Pin Name I/O
1 AINR+
I
2 AINR-
I
3 VREF
O
4 VA
5 AGND
6 AlNL+
I
7 AINL-
I
8 TST1
10 TST2
11 TST3
14 TST4
9 HPFE
I
12 VD
13 DGND
16 PD
I
17 MCLK I
18 SCLK I/O
19 LRCK I/O
20 FSYNC I/O
21 SDATA O
22 CMODE I
23 SMODE1 I
15 SMODE2 I
24 VB
SCLK LRCK FSYNC
23 18 19 20
21
Serial Output
SDATA
Interface
Digital Decimation
Filter
10 11 14
18
PIN / FUNCTION
Right channel analog positive input pin
Right channel analog negative input pin
Voltage Reference output pin (VA-2.6V)
Normally connected to VA with a 0.1uF ceramic capacitor in
parallel with a 10uF electrolytic capacitor.
Analog section Analog Power Supply, +5V
Analog section Analog Ground
Left channel analog positive input pin
Left channel analog negative input pin
Test pin Should be left floating.
Test pin Should be left floating.
Test pin Should be left floating.
Test pin Should be left floating.
High Pass Filter Enable pin (Pull- up pin)
"H": ON
"H": OFF
Digital section Digital Power Supply pin, +5V
Digital section Digital Ground pin
Power Down pin
"L" brings the device into power-down mode. Must be done
once after power-on.
Master Clock input pin
CMODE="H" : 384fs
CMODE="L" : 256fs
Serial Data Clock pin
Data is clocked out at the falling edge of SCLK.
Slave mode: 64fs clock is input usually.
Master mode: SCLK outputs a 64fs clock.
SCLK stays low during the power-down mode(PD="L").
L/R Channel Clock Select pin
Slave mode: An fs clock is fed to this LRCK pin.
Master mode: LRCK output an fs clock.
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H"
during reset when SMODE1 "H".
Frame Synchronization Signal pin
S!ave mode: When "H", data bits are clocked out on SDATA.
2
As I S slave mode ignores FSYNC It should hold "L" or
"H".
Master mode: FSYNC outputs 2fs clock.
Stay low during the power-down mode(PD="L") .
Serial Data Output pin
Data are output with MSB first, in 2's complement format.
After 20 bits are output it turns to "L". It also remains "L" at a
power- down mode(PD="L").
Master Clock Selection pin
"L": MCLK=256fs
"H": MCLK=384fs
Serial Interface Mode Select pin
Defines the directions of LRCK, SCLK and FSYNC pins and
Output Data Format. SMODE2 is pull- down pin.
SMODE1 SMODE2 MODE
L L Slave mode: MSB justified : H/L
H L Master mode Similar to I
L H Slave mode: I
H H Master mode: I
Substrate Power Supply, +5V
Figure 7-11
(Pull- down pin)
(Pull- down pin)
(Pull- down pin)
(Pull- down pin)
LRCK
2
S : H/L
2
S : L/H
2
S : L/H