IBM System/34 Maintenance Manual page 176

1'''---'·
Control
Processor Status
• Address compare (high byte and compare logic)
• Branch on condition
• Storage data register (SDR) (bits 4 through 7)
• Decode logic
• Processor condition register (PCR) and controls
• Processor check register
• Display bits 0 through 7, P (high byte)
• Input/output immediate decodes (control processor)
• Assembly bus
Console switches 1 and 2
Event indicators
Processing unit checks
Processor condition register (PCR)
Control processor bus out high byte
Control
Processor Status 2
'-..JI •
Input/output clocks
• Address compare (low byte and compare logic)
• Run latch
• Stop latch (main storage processor)
• Input/output immediate decodes (main storage
processor)
• Display bits 12 through 15, P
(-- • Assembly bus
\ . . . . . . _/ Console switches 3 and 4
Console status
Input/output clock low byte
Input/output clock high byte
• Machine check latch and processor check trigger
• System in use indicator driver
• Stop indicator driver
Control
Processor
Channel
• Channel register
• Channel controls
• Channel clocks
• Channel checks
• Channel interrupt
• Channel status
• Cycle steal control
•
15-110
Processing Unit 5