Signal Flow Block Diagram - Crown IQ-PIP-USP3 Reference Manual

Programmable input processor with tcp/iq

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Figure 4.1 shows the system block diagram. Figure 4.2 shows the input routing screen.

Note that there are two pairs of "source" selectors - each allows selection of 1, 2 or the sum

of both for both Analog and CobraNet Inputs. What goes into each of the input channel

paths is one of a selection of four possible input configurations of the channel pair.

Figure 4.1 Signal Flow Block Diagram

Figure 4.2 Input Routing Screen

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