Silicon Laboratories SiM3U1xx Manual page 4

SiM3U1xx
4.6.5. SPI (SPI0, SPI1) .................................................................................................. 47
4.6.6. I2C (I2C0, I2C1)................................................................................................... 47
4.6.7. I2S (I2S0)............................................................................................................. 48
4.7. Analog .......................................................................................................................... 49
4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1).............................. 49
4.7.2. Sample Sync Generator (SSG0) ......................................................................... 49
4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) ............................................ 49
4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) ............................ 50
4.7.5. Low Current Comparators (CMP0, CMP1) .......................................................... 50
4.7.6. Current-to-Voltage Converter (IVC0) ................................................................... 50
4.8. Reset Sources..............................................................................................................51
4.9. Security ........................................................................................................................ 52
4.10.On-Chip Debugging ..................................................................................................... 52
5. Pin Definitions and Packaging Information.....................................................................53
5.1. SiM3U1x7 Pin Definitions............................................................................................. 53
5.2. SiM3U1x6 Pin Definitions............................................................................................. 61
5.3. SiM3U1x4 Pin Definitions............................................................................................. 68
6. Ordering Information .........................................................................................................72
6.1. LGA-92 Package Specifications...................................................................................74
6.1.1. LGA-92 Solder Mask Design ............................................................................... 76
6.1.2. LGA-92 Stencil Design ........................................................................................ 76
6.1.3. LGA-92 Card Assembly ....................................................................................... 76
6.2. TQFP-80 Package Specifications ................................................................................ 77
6.2.1. TQFP-80 Solder Mask Design............................................................................. 80
6.2.2. TQFP-80 Stencil Design ...................................................................................... 80
6.2.3. TQFP-80 Card Assembly..................................................................................... 80
6.3. QFN-64 Package Specifications .................................................................................. 81
6.3.1. QFN-64 Solder Mask Design............................................................................... 83
6.3.2. QFN-64 Stencil Design ........................................................................................ 83
6.3.3. QFN-64 Card Assembly....................................................................................... 83
6.4. TQFP-64 Package Specifications ................................................................................ 84
6.4.1. TQFP-64 Solder Mask Design............................................................................. 87
6.4.2. TQFP-64 Stencil Design ...................................................................................... 87
6.4.3. TQFP-64 Card Assembly..................................................................................... 87
6.5. QFN-40 Package Specifications .................................................................................. 88
6.5.1. QFN-40 Solder Mask Design............................................................................... 90
6.5.2. QFN-40 Stencil Design ........................................................................................ 90
6.5.3. QFN-40 Card Assembly....................................................................................... 90
7. Revision Specific Behavior............................................................................................... 91
7.1. Revision Identification .................................................................................................. 91
7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1)...................... 92
7.2.1. Problem ...............................................................................................................92
7.2.2. Impacts ................................................................................................................ 92
7.2.3. Workaround ......................................................................................................... 92
7.2.4. Resolution............................................................................................................ 92
Contact Information ................................................................................................................ 94
4 Preliminary Rev. 0.8