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32-bit ARM® Cortex™-M3 CPU
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80 MHz maximum frequency
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Single-cycle multiplication, hardware division support
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Nested vectored interrupt control (NVIC) with 16 levels of
interrupt priority
Memory
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32–256 kB Flash, in-system programmable
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8–32 kB SRAM (including 4 kB retention SRAM)
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External bus interface supports up to 16 MB of external mem-
ory and a parallel LCD interface with QVGA resolution
Power Management
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Low drop-out (LDO) regulator
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Power-on reset circuit and brownout detectors
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5-to-3.3 V voltage regulator supports up to 150 mA to drive the
device directly from USB; no off-chip regulator required
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Programmable external regulator supports up to 3.6 V,
1000 mA
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Multiple power modes supported for low power optimization
Clock Sources
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Internal oscillator with PLL: Fine frequency resolution up to
80 MHz; spread-spectrum mode for reduced EMI
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USB internal 48 MHz oscillator supports crystal-less operation
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Low power internal oscillator: 20 MHz and 2.5 MHz modes
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Low frequency internal oscillator: 16.4 kHz
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External oscillators: Crystal, RC, C, CMOS and RTC Crystal
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Flexible clock divider: Reduce frequency by up to 128x from
any clock source
128/192/256-bit Hardware AES Encryption
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Hardware-supported Electronic Codebook (ECB), Cipher-Block
Chaining (CBC) and Counter (CTR) algorithms
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All cipher operations can be performed without any firmware
intervention for a set of 4-word blocks (up to 32 kB)
16/32-bit CRC
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Hardware support for common 32-bit and 16-bit polynomials
Timers/Counters
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2 x 32-bit or 4 x 16-bit timers with capture/compare
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2 x 16-bit, 2-channel counters with capture/compare/PWM
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16-bit, 6-channel counter with capture/compare/PWM and
dead-time controller with differential outputs
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16-bit low power timer/pulse counter operational in the lowest
power mode
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32-bit real time clock (RTC) with multiple alarms
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Watchdog timer
Current-to-Voltage Converter
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Supports up to 6 mA input range
Supply Voltage
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2.7 to 5.5 V (regulator enabled)
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1.8 to 3.6 V (regulator disabled)
Preliminary Rev. 0.8 2/12
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
High-Performance, Low-Power, 32-Bit Precision32™
Low Power Features
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85 nA current mode with voltage supply monitor enabled
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350 nA current mode with RTC (internal oscillator)
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620 nA current mode with RTC (external oscillator)
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10 µs wakeup (lowest power mode); 1.5 µs analog setting time
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275 µA/MHz active current
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Clocks can be gated off from unused peripherals to save power
2 x 12-Bit Analog-to-Digital Converters
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Up to 28 input channels
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Up to 250 ksps 12-bit mode or 1 Msps 10-bit mode
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Single, simultaneous, and interleaving modes supported
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Channel sequencer enables automatic multiplexing of multiple
channels without firmware intervention
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Internal VREF or external VREF supported
2 x 10-Bit Digital-to-Analog Converters
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DMA support for waveform generation
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Four-word circular buffer to enable 12-bit mode
16-Channel Capacitance-to-Digital Converter
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Supports buttons, sliders, wheels, and capacitive proximity
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Fast conversion time; <1 µA wake-on-touch average current
Two Low-Current Comparators
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Integrated 6-bit programmable reference voltage
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400 nA current consumption in low power mode
16-Channel DMA Controller
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Supports ADC, DAC, USB, I2C, I
capacitive sensing, external triggers, and timers
Up to 65 Flexible I/O
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Up to 59 contiguous GPIO with two priority crossbars providing
flexibility in pin assignments; 12 x 5 V tolerant GPIO
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Up to 6 programmable high drive capable (5–300 mA, 1.8–6 V)
I/O can drive LEDs, power MOSFETs, buzzers, etc.
Communication Interfaces
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USB 2.0-compliant full speed with 10 endpoints, 2 kB buffer,
oscillator with automatic frequency correction, and transceiver;
no external components needed
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2 x USARTs and 2 x UARTs with IrDA and ISO7816 SmartCard
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3 x SPIs, 2 x I2C, I
On-Chip Debugging
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Serial wire debug (SWD) and JTAG allow for full-speed, non-
intrusive debug
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Serial wire viewer (SWV) available in 64 / 80 / 92-pin packages
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Cortex-M3 embedded trace macrocell (ETM) in 80 / 92-pin
packages
Temperature Range: –40 to +85 °C
Package Options
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QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm)
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TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm)
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LGA option: 92-pin (7 x 7 mm)
Copyright © 2012 by Silicon Laboratories
USB MCU Family with up to 256 kB of Flash
2
S, SPI, USART, AES, EPCA,
2
S (receive and transmit)
SiM3U1xx
SiM3U1xx
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Table of Contents
Related Manuals for Silicon Laboratories SiM3U1xx
Summary of Contents for Silicon Laboratories SiM3U1xx
- Page 1 TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm) LGA option: 92-pin (7 x 7 mm) Preliminary Rev. 0.8 2/12 Copyright © 2012 by Silicon Laboratories SiM3U1xx This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
- Page 2 SiM3U1xx Preliminary Rev. 0.8...
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Page 3: Table Of Contents
3. Electrical Specifications......................9 3.1. Electrical Characteristics ....................9 3.2. Thermal Conditions ...................... 33 3.3. Absolute Maximum Ratings..................33 4. Precision32™ SiM3U1xx System Overview ..............35 4.1. Power ........................... 37 4.1.1. LDO and Voltage Regulator (VREG0) ..............37 4.1.2. Voltage Supply Monitor (VMON0) ............... 37 4.1.3. - Page 4 SiM3U1xx 4.6.5. SPI (SPI0, SPI1) ....................47 4.6.6. I2C (I2C0, I2C1)....................47 4.6.7. I2S (I2S0)......................48 4.7. Analog .......................... 49 4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1)......49 4.7.2. Sample Sync Generator (SSG0) ................. 49 4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) ..........49 4.7.4.
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Page 5: Related Documents And Conventions
1.1.2. Hardware Access Layer (HAL) API Description The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read each bit in the SiM3U1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual. 1.1.3. ARM Cortex-M3 Reference Manual The ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex-M3 reference documentation. -
Page 6: Typical Connection Diagrams
This section provides typical connection diagrams for SiM3U1xx devices. 2.1. Power Figure 2.1 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator is in use and USB is not used. SiM3U1xx Device... - Page 7 Figure 2.3. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered) Figure 2.4 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator used and USB is connected (self-powered). The VBUS signal is used to detect when USB is connected to a host device.
- Page 8 SiM3U1xx SiM3U1xx Device USB 5 V (in) VBUS 3.3-6 V (in) VREGn VREGIN 3.3 V (out) VIOHD 1 uF and 0.1 uF bypass capacitors required for each power pin placed 1.8-3.3 V (in) as close to the pins as possible.
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Page 9: Electrical Specifications
SiM3U1xx 3. Electrical Specifications 3.1. Electrical Characteristics All electrical parameters in all tables are specified under the conditions listed in Table 3.1, unless stated otherwise. Table 3.1. Recommended Operating Conditions Parameter Symbol Conditions Units Operating Supply Voltage on VDD —... - Page 10 SiM3U1xx Table 3.2. Power Consumption Parameter Symbol Conditions Units Digital Core Supply Current 2,3,4,5 Normal Mode —Full speed = 80 MHz, — 36.5 with code executing from Flash, = 40 MHz peripheral clocks ON = 48 MHz — 28.5 = 20 MHz —...
- Page 11 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Conditions Units Power Mode 3 = 1.8 V, T = 25 °C — — µA = 3.0 V, T = 25 °C — — µA Power Mode 9 —Low Power RTC Disabled, —...
- Page 12 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Conditions Units Analog Peripheral Supply Currents Voltage Regulator (VREG0) Normal Mode, T = 25 °C — — µA VREGIN BGDIS = 0, SUSEN = 0 Normal Mode, T = 85 °C —...
- Page 13 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Conditions Units External Oscillator (EXTOSC0) FREQCN = 111 — EXTOSC FREQCN = 110 — µA FREQCN = 101 — µA FREQCN = 100 — µA FREQCN = 011 — µA FREQCN = 010 —...
- Page 14 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Conditions Units Flash Current on VDD Write Operation — — FLASH-W Erase Operation — — FLASH-E Notes: 1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
- Page 15 SiM3U1xx Table 3.4. Reset and Supply Monitor Parameter Symbol Conditions Units High Supply Monitor Threshold Early Warning 2.10 2.20 2.30 VDDMH (VDDHITHEN = 1) Reset 1.95 2.05 Low Supply Monitor Threshold Early Warning 1.81 1.85 1.88 VDDML (VDDHITHEN = 0) Reset 1.70...
- Page 16 Output Load Regulation BGDIS = 0 — mV/mA DDLR Output Capacitance — µF *Note: Total current VREG0 is capable of providing. Any current consumed by the SiM3U1xx reduces the current available to external devices powered from VDD. Preliminary Rev. 0.8...
- Page 17 SiM3U1xx Table 3.6. External Regulator Parameter Symbol Conditions Units Input Voltage Range (at VRE- — REGIN GIN) Output Voltage (at Programmable in — EXREGOUT EXREGOUT) 100 mV steps NPN Current Drive 400 mV Dropout — — PNP Current Drive > V —...
- Page 18 SiM3U1xx Table 3.7. Flash Memory Parameter Symbol Conditions Units Write Time One 16-bit Half Word µs WRITE Erase Time One Page ERASE Full Device ERALL Voltage During Programming — PROG Endurance (Write/Erase Cycles) — Cycles Retention = 85 °C, 1k Cycles —...
- Page 19 SiM3U1xx Table 3.8. Internal Oscillators (Continued) Parameter Symbol Conditions Units Lock Time = 48 MHz, — — µs PLL0LOCK = 80 MHz, PLL0OSC M=59, N= 99, LOCKTH = 0 = 20 MHz, — — µs = 80 MHz, PLL0OSC M=24, N=99,...
- Page 20 SiM3U1xx Table 3.8. Internal Oscillators (Continued) Parameter Symbol Conditions Units Low Power Oscillator (LPOSC0) Oscillator Frequency Full Temperature and LPOSC Supply Range = 25 °C, 19.6 20.4 = 3.3 V Divided Oscillator Frequency Full Temperature and 2.375 2.625 LPOSCD Supply Range Power Supply Sensitivity = 25 °C...
- Page 21 SiM3U1xx Table 3.10. SAR ADC Parameter Symbol Conditions Units Resolution 12 Bit Mode Bits bits 10 Bit Mode Bits Supply Voltage Requirements High Speed Mode — (VDD) Low Power Mode — Throughput Rate 12 Bit Mode — — ksps (High Speed Mode) 10 Bit Mode —...
- Page 22 SiM3U1xx Table 3.10. SAR ADC (Continued) Parameter Symbol Conditions Units Offset Error (using AGND) 12 Bit Mode, VREF =2.4 V –2 10 Bit Mode, VREF =2.4 V –1 Offset Temperatue Coefficient — 0.004 — LSB/°C Slope Error 12 Bit Mode –0.07...
- Page 23 SiM3U1xx Table 3.11. IDAC Parameter Symbol Conditions Units Static Performance Resolution Bits bits Integral Nonlinearity — ±0.5 ±2 Differential Nonlinearity (Guaranteed — ±0.5 ±1 Monotonic) Output Compliance Range — — – 1.0 Full Scale Output Current 2 mA Range 2.046 2.10...
- Page 24 SiM3U1xx Table 3.12. Capacitive Sense Parameter Symbol Conditions Units Single Conversion Time 12-bit Mode — — µs single (Default Configuration) 13-bit Mode — — µs 14-bit Mode — — µs 16-bit Mode — — µs Maximum External Capacitive Load Highest Gain Setting —...
- Page 25 SiM3U1xx Table 3.14. Voltage Reference Electrical Characteristics – = 1.8 to 3.6 V, 40 to +85 °C unless otherwise specified. Parameter Symbol Conditions Units Internal Fast Settling Reference Output Voltage –40 to +85 °C, 1.62 1.65 1.68 REFFS = 1.8–3.6 V Temperature Coefficient —...
- Page 26 SiM3U1xx Table 3.15. Temperature Sensor Parameter Symbol Conditions Units Offset = 0 °C — — Offset Error* = 0 °C — ±14 — Slope — — mV/°C Slope Error* — — µV/°C Linearity — — °C Turn-on Time — —...
- Page 27 SiM3U1xx Table 3.16. Comparator Parameter Symbol Conditions Units Response Time, CMPMD = 00 +100 mV Differential — — RESP0 (Highest Speed) –100 mV Differential — — Response Time, CMPMD = 11 +100 mV Differential — — µs RESP3 (Lowest Power) –100 mV Differential...
- Page 28 SiM3U1xx Table 3.16. Comparator (Continued) Parameter Symbol Conditions Units Positive Hysterisis CMPHYP = 00 — 1.37 — Mode 3 (CPMD = 11) CMPHYP = 01 — — CMPHYP = 10 — — CMPHYP = 11 — 15.6 — Negative Hysterisis CMPHYN = 00 —...
- Page 29 SiM3U1xx Table 3.17. USB Transciever Parameter Symbol Conditions Units Valid Supply Range — (for USB Compliance) = 5 V, V = 3.3 V VBUS Pull-Down Leakage Current — — µA VBUSL Transmitter Output High Voltage — — Output Low Voltage —...
- Page 30 SiM3U1xx Table 3.18. Port I/O Parameter Symbol Conditions Units Standard I/O (PB0, PB1, and PB2) and 5 V Tolerant I/O (PB3) Output High Voltage Low Drive, I = –2 mA – 0.7 — — High Drive, I = –5 mA –...
- Page 31 SiM3U1xx Table 3.18. Port I/O (Continued) Parameter Symbol Conditions Units Output Fall Time Slew Rate Mode 0, — — = 5V IOHD Slew Rate Mode 1, — — = 5V IOHD Slew Rate Mode 2, — — µs = 5V...
- Page 32 SiM3U1xx Table 3.18. Port I/O (Continued) Parameter Symbol Conditions Units P-Channel Source Current Limit Mode 0 — 0.88 — SRCL (2.7 V <= VIOHD <= 6 V, Mode 1 — 1.17 — = VIOHD - 0.8V) Mode 2 — 1.76 —...
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Page 33: Thermal Conditions
SiM3U1xx 3.2. Thermal Conditions Table 3.19. Thermal Conditions Parameter Symbol Conditions Units Thermal Resistance* — — °C/W LGA-92 Packages — — °C/W TQFP-80 Packages — — °C/W QFN-64 Packages — — °C/W TQFP-64 Packages — — °C/W QFN-40 Packages *Note: Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad. - Page 34 SiM3U1xx Table 3.20. Absolute Maximum Ratings (Continued) Parameter Symbol Conditions Units Voltage on I/O pins, Port Bank 3 I/O SiM3U1x7, PB3.0– –0.3 PB3.7, V > 3.3 V SiM3U1x7, PB3.0– –0.3 +2.5 PB3.7, V < 3.3 V SiM3U1x7, PB3.8 - –0.3 Lowest of PB3.11...
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Page 35: Precision32™ Sim3U1Xx System Overview
SiM3U1xx 4. Precision32™ SiM3U1xx System Overview The SiM3U1xx Precision32™ devices are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 6.1 for specific product feature selection and part ordering numbers. Core: 32-bit ARM Cortex-M3 CPU. - Page 36 Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RESET pins are powered from the IO supply voltage. The SiM3U1xx devices are available in 40-pin or 64- pin QFN, 64-pin or 80-pin TQFP, or 92-pin LGA packages.
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Page 37: Power
4.1.4. Power Management Unit (PMU) The Power Management Unit on the SiM3U1xx manages the power systems of the device. On power-up, the PMU ensures the core voltages are a proper value before core instruction execution begins. It also recognizes and manages the various wake sources for low-power modes of the device. -
Page 38: Device Power Modes
SiM3U1xx 4.1.5. Device Power Modes The SiM3U1xx devices feature four low power modes in addition to normal operating mode. Several peripherals provide wake up sources for these low power modes, including the Low-Power Timer (LPT0), RTC0 (alarms and oscillator failure notification), Comparator 0, and PMU Pin Wake. All power modes are detailed in Table 4.1. - Page 39 SiM3U1xx 4.1.5.1. Normal Mode Normal mode encompasses the typical full-speed operation. The power consumption of the device in this mode will vary depending on AHB/APB clock speeds and the settings of CLKCTRL and the peripherals. 4.1.5.2. Power Mode 1 Power Mode 1 occurs when the core executes code from RAM instead of Flash. The power consumption of the device is slightly less than normal mode when in PM1.
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Page 40: I/O
The 5 V tolerant pins can be connected to external circuitry operating at voltages above the device supply without needing extra components to shift the voltage level. 4.2.4. Crossbars The SiM3U1xx devices have two Crossbars with the following features: Flexible peripheral assignment to port pins. -
Page 41: Clocking
SiM3U1xx 4.3. Clocking The SiM3U1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and is derived from one of seven sources: the RTC0 Oscillator, the Low Frequency Oscillator, the Low Power Oscillator, the divided Low Power Oscillator, the External Oscillator, the PLL0 Oscillator, and the USB0 Oscillator. In addition, a divider for the AHB clock provides flexible clock options for the device. -
Page 42: Pll (Pll0)
Ability to suspend all output frequency updates (including dithering and spectrum spreading) using the STALL bit during jitter-sensitive operations. 4.3.2. Low Power Oscillator (LPOSC0) The Low Power Oscillator is the default AHB oscillator on SiM3U1xx devices and enables or disables automatically, as needed. The Low Power Oscillator has the following features: ... -
Page 43: Data Peripherals
SiM3U1xx 4.4. Data Peripherals 4.4.1. 16-Channel DMA Controller The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the system, as the device can spend more time in low-power modes. -
Page 44: Counters/Timers And Pwm
4.5. Counters/Timers and PWM 4.5.1. Programmable Counter Array (EPCA0, PCA0, PCA1) The SiM3U1xx devices include two types of PCA module: Enhanced and Standard. The Enhanced Programmable Counter Array (EPCA0) and Standard Programmable Counter Array (PCA0, PCA1) modules are timer/counter systems allowing for complex timing or waveform generation. Multiple modules run from the same main counter, allowing for synchronous output waveforms. -
Page 45: Real-Time Clock (Rtc0)
32.768 kHz watch crystal. The RTC0 provides three alarm events in addition to a missing clock event, which can also function as interrupt, reset, or wakeup sources on SiM3U1xx devices. The RTC0 module includes internal loading capacitors that are programmable to 16 discrete levels, allowing compatibility with a wide range of crystals. -
Page 46: Communications Peripherals
SiM3U1xx 4.6. Communications Peripherals 4.6.1. External Memory Interface (EMIF0) The External Memory Interface (EMIF0) allows external parallel asynchronous devices, like SRAMs and LCD controllers, to appear as part of the system memory map. The EMIF0 module includes the following features: ... -
Page 47: Uart (Uart0, Uart1)
SiM3U1xx IrDA modulation and demodulation with programmable pulse widths. Smartcard ACK/NACK support. Parity error, frame error, overrun, and underrun detection. Multi-master and half-duplex support. Multiple loop-back modes supported. Multi-processor communications support. 4.6.4. UART (UART0, UART1) The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single device. -
Page 48: I2S (I2S0)
SiM3U1xx The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/ stop control and generation. -
Page 49: Analog
SiM3U1xx 4.7. Analog 4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1) The SARADC0 and SARADC1 modules on SiM3U1xx devices are Successive Approximation Register (SAR) Analog to Digital Converters (ADCs). The key features of the SARADC module are: Single-ended 12-bit and 10-bit modes. -
Page 50: 16-Channel Capacitance-To-Digital Converter (Capsense0)
SiM3U1xx 4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) The Capacitance Sensing module measures capacitance on external pins and converts it to a digital value. The CAPSENSE module has the following features: Multiple start-of-conversion sources (CSnTx). Option to convert to 12, 13, 14, or 16 bits. -
Page 51: Reset Sources
SiM3U1xx 4.8. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: The core halts program execution. Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. -
Page 52: Security
SiM3U1xx 4.9. Security The peripherals on the SiM3U1xx devices have a register lock and key mechanism that prevents any undesired accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A key sequence must be written in order to the KEY register to modify any of the bits in PERIPHLOCKx. Any subsequent write to KEY will then inhibit any accesses of PERIPHLOCKx until it is unlocked again through KEY. -
Page 53: Pin Definitions And Packaging Information
SiM3U1xx 5. Pin Definitions and Packaging Information 5.1. SiM3U1x7 Pin Definitions PB4.5 PB0.12 PB4.4 PB0.13 PB4.3 PB0.14 VSSHD PB0.15 VIOHD PB1.0 PB4.2 PB1.1 PB4.1 PB1.2/TRST PB4.0 PB1.3/TDO/SWV PB3.11 PB1.4/TDI PB3.10 PB1.5/ETM0 80-Pin TQFP PB3.9 PB1.6/ETM1 PB3.8 PB3.7 PB1.7/ETM2 PB3.6 PB1.8/ETM3 PB3.5... - Page 54 SiM3U1xx PB4.5 PB0.12 PB4.4 PB0.13 PB4.3 PB0.14 VIOHD PB0.15 VSSHD PB4.2 PB1.0 PB1.1 PB3.11 PB4.1 PB1.2* PB1.3* PB3.10 PB1.4* PB4.0 92 pin LGA PB1.5* PB3.9 (Top View) PB1.6* PB3.8 PB1.7* PB3.7 PB3.6 PB1.8* PB3.5 PB1.9* PB3.4 SWCLK* PB3.3 SWDIO* PB3.2 PB1.10...
- Page 55 SiM3U1xx Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 Pin Name Type Ground Power (Core) 74 A44 Power (I/O) VREGIN Power (Regulator) 76 A45 VSSHD Ground (High Drive) VIOHD Power (High Drive) RESET Active-low Reset 80 A48 D– USB Data-...
- Page 56 SiM3U1xx Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) Pin Name Type PB0.7 Standard I/O 65 B29 XBR0 ADC0.6 CS0.6 IVC0.0 PB0.8 Standard I/O 64 A39 XBR0 ADC0.7 CS0.7 IVC0.1 PB0.9 Standard I/O 63 A38 XBR0 ADC0.8...
- Page 57 SiM3U1xx Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) Pin Name Type PB1.8/ETM3 Standard I/O /ETM 47 B21 XBR0 ADC1.10 CS0.9 PB1.9/ Standard I/O /ETM 46 A28 XBR0 ADC1.9 TRACECLK PB1.10 Standard I/O 43 A26 XBR0...
- Page 58 SiM3U1xx Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) Pin Name Type PB2.5 Standard I/O 30 A18 XBR1 AD12m / LSI5 Yes INT0.5 INT1.5 PB2.6 Standard I/O 29 B13 XBR1 AD11m/ INT0.6 INT1.6 PB2.7 Standard I/O...
- Page 59 SiM3U1xx Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) Pin Name Type PB3.4 5 V Tolerant I/O A9 XBR1 INT0.9 CMP0P.4 INT1.9 CMP1P.4 WAKE.8 PB3.5 5 V Tolerant I/O B7 XBR1 ALEm DAC0T2 CMP0N.4 DAC1T2 CMP1N.4 INT0.10...
- Page 60 SiM3U1xx Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) Pin Name Type PB4.0 High Drive I/O LSO0 PB4.1 High Drive I/O LSO1 PB4.2 High Drive I/O LSO2 PB4.3 High Drive I/O LSO3 PB4.4 High Drive I/O LSO4 PB4.5...
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Page 61: Sim3U1X6 Pin Definitions
SiM3U1xx 5.2. SiM3U1x6 Pin Definitions PB4.3 PB0.9 VSSHD PB0.10 VIOHD PB0.11 PB4.2 PB0.12 PB4.1 PB0.13 PB4.0 PB0.14/TDO/SWV PB3.9 PB0.15/TDI PB3.8 PB1.0 64 Pin TQFP PB3.7 PB1.1 PB3.6 PB3.5 PB1.2 PB3.4 PB1.3 PB3.3 SWCLK/TCK PB3.2 SWDIO/TMS PB3.1 PB1.4 PB3.0 PB1.5 Figure 5.3. SiM3U1x6-GQ Pinout... - Page 62 SiM3U1xx PB4.3 PB0.9 VSSHD PB0.10 VIOHD PB0.11 PB4.2 PB0.12 PB4.1 PB0.13 PB4.0 PB0.14/TDO/SWV PB3.9 PB0.15/TDI PB3.8 PB1.0 64 pin QFN PB3.7 (TopView) PB1.1 PB3.6 PB3.5 PB1.2 PB3.4 PB1.3 PB3.3 SWCLK/TCK PB3.2 SWDIO/TMS PB3.1 PB1.4 PB3.0 PB1.5 Figure 5.4. SiM3U1x6-GM Pinout...
- Page 63 SiM3U1xx Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 Pin Name Type Ground Power (Core) Power (I/O) VREGIN Power (Regulator) VSSHD Ground (High Drive) VIOHD Power (High Drive) RESET Active-low Reset USB Data- USB Data+ VBUS USB Bus Sense...
- Page 64 SiM3U1xx Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) Pin Name Type PB0.6 Standard I/O XBR0 ADC0.8 CS0.7 RTC1 PB0.7 Standard I/O XBR0 RTC2 PB0.8 Standard I/O XBR0 ADC0.9 VREFGND PB0.9 Standard I/O XBR0 ADC0.10...
- Page 65 SiM3U1xx Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) Pin Name Type PB1.7 Standard I/O XBR0 AD15m/ ADC1T15 ADC1.4 WAKE.1 CS0.11 PB1.8 Standard I/O XBR0 AD14m/ WAKE.2 ADC1.3 CS0.12 PB1.9 Standard I/O XBR0 AD13m/ WAKE.3 ADC1.2...
- Page 66 SiM3U1xx Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) Pin Name Type PB3.1 5 V Tolerant I/O XBR1 AD1m/ CMP0N.1 CMP1N.1 PB3.2 5 V Tolerant I/O XBR1 AD0m/ DAC0T0 CMP0P.2 DAC1T0 CMP1P.2 LPT0T0 WAKE.8 PB3.3...
- Page 67 SiM3U1xx Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) Pin Name Type PB3.9 5 V Tolerant I/O XBR1 DAC0T6 CMP0N.5 DAC1T6 CMP1N.5 LPT0T2 EXREGBD INT0.10 INT1.10 WAKE.15 PB4.0 High Drive I/O LSO0 PB4.1 High Drive I/O LSO1 PB4.2...
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Page 68: Sim3U1X4 Pin Definitions
SiM3U1xx 5.3. SiM3U1x4 Pin Definitions PB4.3 PB0.4 VSSHD PB0.5 VIOHD PB0.6 PB4.2 PB0.7 PB4.1 PB0.8 40 pin QFN (Top View) PB4.0 PB0.9 PB3.3 SWCLK PB3.2 SWDIO PB3.1 PB0.10 PB3.0 PB0.11 Figure 5.5. SiM3U1x4-GM Pinout Preliminary Rev. 0.8... - Page 69 SiM3U1xx Table 5.3. Pin Definitions and alternate functions for SiM3U1x4 Pin Name Type Ground Power (Core) Power (I/O) VREGIN Power (Regulator) VSSHD Ground (High Drive) VIOHD Power (High Drive) RESET Active-low Reset USB Data– USB Data+ VBUS USB Bus Sense...
- Page 70 SiM3U1xx Table 5.3. Pin Definitions and alternate functions for SiM3U1x4 (Continued) Pin Name Type PB0.6 Standard I/O XBR0 ADC0.0 CS0.3 XTAL1 PB0.7 Standard I/O XBR0 ADC0.1 CS0.4 XTAL2 PB0.8 Standard I/O XBR0 ADC0.14 ADC1.14 PB0.9 Standard I/O XBR0 ADC0.15...
- Page 71 SiM3U1xx Table 5.3. Pin Definitions and alternate functions for SiM3U1x4 (Continued) Pin Name Type PB3.0 5 V Tolerant I/O XBR1 DAC0T0 CMP0P.1 DAC1T0 CMP1P.1 LPT0T0 EXREGSP INT0.0 INT1.0 WAKE.12 PB3.1 5 V Tolerant I/O XBR1 DAC0T1 CMP0N.1 DAC1T1 CMP1N.1...
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Page 72: Ordering Information
Family – U (USB), C (Core) Core – M3 (Cortex M3) Silicon Labs Figure 6.1. SiM3U1xx Part Numbering All devices in the SiM3U1xx family have the following features: Core: ARM Cortex-M3 with maximum operating frequency of 80 MHz. ... - Page 73 SiM3U1xx Table 6.1. Product Selection Guide SiM3U167-B-GM 256 32 LGA-92 SiM3U167-B-GQ 256 32 TQFP-80 SiM3U166-B-GM 256 32 QFN-64 SiM3U166-B-GQ 256 32 TQFP-64 ...
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Page 74: Lga-92 Package Specifications
SiM3U1xx 6.1. LGA-92 Package Specifications Figure 6.2. LGA-92 Package Drawing Table 6.2. LGA-92 Package Dimensions Dimension Nominal 0.74 0.84 0.94 0.25 0.30 0.35 3.15 3.20 3.25 7.00 BSC 6.50 BSC 4.00 BSC 0.50 BSC 7.00 BSC 6.50 BSC 4.00 BSC —... - Page 75 SiM3U1xx Figure 6.3. LGA-92 Landing Diagram Table 6.3. LGA-92 Landing Diagram Dimensions Dimension Typical 6.50 — 6.50 — 0.50 — — 0.35 — 3.20 — 3.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Page 76: Lga-92 Solder Mask Design
SiM3U1xx 6.1.1. LGA-92 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.1.2. LGA-92 Stencil Design 1. -
Page 77: Tqfp-80 Package Specifications
SiM3U1xx 6.2. TQFP-80 Package Specifications Figure 6.4. TQFP-80 Package Drawing Table 6.4. TQFP-80 Package Dimensions Dimension Nominal — — 1.20 0.05 — 0.15 0.95 1.00 1.05 0.17 0.20 0.27 0.09 — 0.20 14.00 BSC 12.00 BSC 0.50 BSC 14.00 BSC 12.00 BSC... - Page 78 SiM3U1xx Table 6.4. TQFP-80 Package Dimensions (Continued) Dimension Nominal 0.45 0.60 0.75 1.00 Ref 0° 3.5° 7° 0.20 0.20 0.08 0.08 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
- Page 79 SiM3U1xx Figure 6.5. TQFP-80 Landing Diagram Table 6.5. TQFP-80 Landing Diagram Dimensions Dimension 13.30 13.40 13.30 13.40 0.50 BSC 0.20 0.30 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines.
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Page 80: Tqfp-80 Solder Mask Design
SiM3U1xx 6.2.1. TQFP-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.2.2. TQFP-80 Stencil Design 1. -
Page 81: Qfn-64 Package Specifications
SiM3U1xx 6.3. QFN-64 Package Specifications Figure 6.6. QFN-64 Package Drawing Table 6.6. QFN-64 Package Dimensions Dimension Nominal 0.80 0.85 0.90 0.00 0.02 0.05 0.18 0.25 0.30 9.00 BSC 3.95 4.10 4.25 0.50 BSC 9.00 BSC 3.95 4.10 4.25 0.30 0.40 0.50... - Page 82 SiM3U1xx Figure 6.7. QFN-64 Landing Diagram Table 6.7. QFN-64 Landing Diagram Dimensions Dimension 8.90 8.90 0.50 0.30 0.85 4.25 4.25 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines.
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Page 83: Qfn-64 Solder Mask Design
SiM3U1xx 6.3.1. QFN-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.3.2. QFN-64 Stencil Design 1. -
Page 84: Tqfp-64 Package Specifications
SiM3U1xx 6.4. TQFP-64 Package Specifications Figure 6.8. TQFP-64 Package Drawing Table 6.8. TQFP-64 Package Dimensions Dimension Nominal — — 1.20 0.05 — 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 — 0.20 12.00 BSC 10.00 BSC 0.50 BSC 12.00 BSC 10.00 BSC... - Page 85 SiM3U1xx Table 6.8. TQFP-64 Package Dimensions (Continued) Dimension Nominal — — 0.20 — — 0.20 — — 0.08 — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
- Page 86 SiM3U1xx Figure 6.9. TQFP-64 Landing Diagram Table 6.9. TQFP-64 Landing Diagram Dimensions Dimension 11.30 11.40 11.30 11.40 0.50 BSC 0.20 0.30 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines.
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Page 87: Tqfp-64 Solder Mask Design
SiM3U1xx 6.4.1. TQFP-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.4.2. TQFP-64 Stencil Design 1. -
Page 88: Qfn-40 Package Specifications
SiM3U1xx 6.5. QFN-40 Package Specifications Figure 6.10. QFN-40 Package Drawing Table 6.10. QFN-40 Package Dimensions Dimension Nominal 0.80 0.85 0.90 0.00 0.02 0.05 0.18 0.25 0.30 6.00 BSC 4.35 4.50 4.65 0.50 BSC 6.00 BSC 4.35 4.65 0.30 0.40 0.50 0.10... - Page 89 SiM3U1xx Figure 6.11. QFN-40 Landing Diagram Table 6.11. QFN-40 Landing Diagram Dimensions Dimension 5.90 5.90 0.50 0.30 0.85 4.65 4.65 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines.
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Page 90: Qfn-40 Solder Mask Design
SiM3U1xx 6.5.1. QFN-40 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.5.2. QFN-40 Stencil Design 1. -
Page 91: Revision Specific Behavior
SiM3U1xx 7. Revision Specific Behavior This chapter details any known differences from behavior as stated in the device datasheet and reference manual. All known errata for the current silicon revision are rolled into this section at the time of publication. Any errata found after publication of this document will initially be detailed in a separate errata document until this datasheet is revised. -
Page 92: Comparator Rising/Falling Edge Flags In Debug Mode (Cmp0, Cmp1)
SiM3U1xx SiM3U166 SiM3U166 BGNZEB BGNZEB 1142 1142 This first character identifies the device revision Figure 7.3. SiM3U1x6 Revision Information M3U164 BGNZ 1142+ This first character identifies the device revision Figure 7.4. SiM3U1x4 Revision Information 7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1) 7.2.1. - Page 93 SiM3U1xx OTES Preliminary Rev. 0.8...
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Page 94: Contact Information
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