Siemens SIMATIC S7-200 System Manual page 521

Table G-3 Memory Ranges and Features for the S7-200 CPUs
Description
User program size
with run mode edit
without run mode edit
User data size
Process-image input register
Process-image output register
Analog inputs (read only)
Analog outputs (write only)
Variable memory (V)
1
Local memory (L)
Bit memory (M)
Special Memory (SM)
Read only
Timers
Retentive on-delay 1 ms
10 ms
100 ms
On/Off delay 1 ms
10 ms
100 ms
Counters
High-speed counters
Sequential control relays (S)
Accumulator registers
Jumps/Labels
Call/Subroutine
Interrupt routines
Positive/negative transitions
PID loops
Ports
1
LB60 to LB63 are reserved by STEP 7- -Micro/WIN, version 3.0 or later.
CPU 221 CPU 222
4096 bytes 4096 bytes
4096 bytes 4096 bytes
2048 bytes 2048 bytes
I0.0 to I15.7 I0.0 to I15.7
Q0.0 to Q15.7 Q0.0 to Q15.7
AIW0 to AIW30 AIW0 to AIW30
AQW0 to AQW30 AQW0 to AQW30
VB0 to VB2047 VB0 to VB2047
LB0 to LB63 LB0 to LB63
M0.0 to M31.7 M0.0 to M31.7
SM0.0 to SM0.0 to
SM179.7 SM299.7
SM0.0 to SM29.7 SM0.0 to SM29.7
256 (T0 to T255) 256 (T0 to T255)
T0, T64 T0, T64
T1 to T4, and T1 to T4, and
T65 to T68 T65 to T68
T5 to T31, and T5 to T31, and
T69 to T95 T69 to T95
T32, T96 T32, T96
T33 to T36, and T33 to T36, and
T97 to T100 T97 to T100
T37 to T63, and T37 to T63, and
T101 to T255 T101 to T255
C0 to C255 C0 to C255
HC0 to HC5 HC0 to HC5
S0.0 to S31.7 S0.0 to S31.7
AC0 to AC3 AC0 to AC3
0 to 255 0 to 255
0 to 63 0 to 63
0 to 127 0 to 127
256 256
0 to 7 0 to 7
Port 0 Port 0
S7-200 Quick Reference Information
CPU 224XP
CPU 224
CPU 224XPsi
8192 bytes 12288 bytes
12288 bytes 16384 bytes
8192 bytes 10240 bytes
I0.0 to I15.7 I0.0 to I15.7
Q0.0 to Q15.7 Q0.0 to Q15.7
AIW0 to AIW62 AIW0 to AIW62
AQW0 to AQW62 AQW0 to AQW62
VB0 to VB8191 VB0 to VB10239
LB0 to LB63 LB0 to LB63
M0.0 to M31.7 M0.0 to M31.7
SM0.0 to SM0.0 to
SM549.7 SM549.7
SM0.0 to SM29.7 SM0.0 to SM29.7
256 (T0 to T255) 256 (T0 to T255)
T0, T64 T0, T64
T1 to T4, and T1 to T4, and
T65 to T68 T65 to T68
T5 to T31, and T5 to T31, and
T69 to T95 T69 to T95
T32, T96 T32, T96
T33 to T36, and T33 to T36, and
T97 to T100 T97 to T100
T37 to T63, and T37 to T63, and
T101 to T255 T101 to T255
C0 to C255 C0 to C255
HC0 to HC5 HC0 to HC5
S0.0 to S31.7 S0.0 to S31.7
AC0 to AC3 AC0 to AC3
0 to 255 0 to 255
0 to 63 0 to 63
0 to 127 0 to 127
256 256
0 to 7 0 to 7
Port 0 Port 0, Port 1
Appendix G
CPU 226
16384 bytes
24576 bytes
10240 bytes
I0.0 to I15.7
Q0.0 to Q15.7
AIW0 to AIW62
AQW0 to AQW62
VB0 to VB10239
LB0 to LB63
M0.0 to M31.7
SM0.0 to
SM549.7
SM0.0 to SM29.7
256 (T0 to T255)
T0, T64
T1 to T4, and
T65 to T68
T5 to T31, and
T69 to T95
T32, T96
T33 to T36, and
T97 to T100
T37 to T63, and
T101 to T255
C0 to C255
HC0 to HC5
S0.0 to S31.7
AC0 to AC3
0 to 255
0 to 127
0 to 127
256
0 to 7
Port 0, Port 1
507