Vertex Standard VXR-7000 Service Manual page 26

Circuit Description
The DC voltage from the RX Unit is delivered to the
A-D analog input port (pin 31) of the Main CPU Q4012
(HD64F3337YF16) on the CNTL Unit, which compares
the squelch threshold level to that which is memorized in
EEPROM Q4008 (NM93C86A) or set by the front panel
SQL control.
RX PLL and VCO Circuits
The receiver's PLL circuitry consists of PLL subsystem
IC Q3001 (MB15A02PFV1) on the RX Unit, which con-
tains a reference oscillator/divider, serial-to-parallel data
latch, programmable divider, phase comparator and a swal-
low counter. Stability is obtained by a regulated 5 VDC
supply via Q3021 (NJM78L05UA) and temperature com-
pensated 14.4 MHz crystal oscillator X3001 via thermistor
TH3001 and TH3002.
The RX VCO, consisting of FET Q3008 and varactor
diodes D3005, D3006, D3008, and D3009, oscillates be-
tween 376.65 MHz and 406.65 MHz according to the pro-
grammed receiving frequency. The RX VCO output pass-
es through buffer amplifier Q3009 and first local amplifi-
er Q3011 to the first mixer D3011, as described previous-
ly. A portion of the RX VCO output is applied to the pres-
caler/swallow counter section in the PLL IC, Q3001. There
the RX VCO signal is divided by 64 or 65, according to a
control signal from the Main CPU Q4012 on the CNTL
Unit, before being applied to the programmable divider
section of the PLL IC Q3001.
The data latch section of the PLL IC Q3001 also re-
ceives serial dividing data from the Main CPU Q4012,
which causes the pre-divided RX VCO signal to be fur-
ther divided by 75,330 ~ 81,330 (or 60,264 ~ 65,064) in
the programmable divider section in the PLL IC Q3001,
depending upon the desired receive frequency, so as to
produce a 5 kHz (or 6.25 kHz) derivative of the current
RX VCO frequency. Meanwhile, the reference divider sec-
tion of the PLL IC Q3001 divides the 14.4 MHz crystal
reference from the reference oscillator X3001 and Q3002
(2SC4116GR) by 2880 (or 2304) to produce the 5 kHz
(or 6.25 kHz) loop reference.
The 5 kHz or 6.25 kHz signal from the programmable
divider (derived from the RX VCO) and that derived from
the crystal are applied to the phase detector section of the
PLL IC Q3001, which produces a pulsed output with pulse
duration depending on the phase difference between the
input signals. This pulse train is then converted to DC,
low pass filtered, then fed back to the RX VCO varactor
diodes D3005, D3006, D3008, and D3009.
26
Changes in the DC voltage applied to the varactor di-
odes D3005, D3006, D3008, and D3009 affect the reac-
tance in the tank circuit RX VCO Q3008, changing the
oscillating frequency according to the phase difference
between the signals derived from the RX VCO and the
crystal reference oscillator. The RX VCO is thus phase-
locked to the reference frequency standard.
Transmit Signal Path
The speech audio from the CNTL Unit is applied to
the varactor diode D2008 (HVU350), which frequency
modulates the TX VCO from the unmodulated carrier at
the transmit frequency. The modulated transmit signal is
buffered by Q2008 (2SC5226), then passes through the
RF amplifier Q2010 (2SC3357) and RF diode switch
D2010 (RN739F) to the PA Unit.
The transmit signal is applied to the RF amplifier
Q1501 (2SC3357) and RF power module IC Q1502
(PF0342A), then finally amplified by power amplifier
Q1507 (2SC3102) up to 50 Watts. Harmonic and spuri-
ous radiation in the final output is suppressed by a low
pass filter consisting of coils L1508 ~ L1511, plus capac-
itors C1548, C1555, C1557, C1561, C1567, and C1566
on the PA Unit, before delivery to the TX antenna jack.
TX PLL and VCO Circuits
The Transmitter's PLL circuitry consists of PLL sub-
system IC Q2001 (MB15A02PFV1) on the RX Unit,
which contains a reference oscillator/divider, serial-to-
parallel data latch, programmable divider, phase compar-
ator and a swallow counter. Stability is obtained by a reg-
ulated 5 VDC supply via Q2012 (NJM78L05UA) and
temperature compensated 14.4 MHz crystal oscillator
X2001 via thermistor TH2001, TH2002 and TH2003.
The TX VCO, consisting of FET Q2005 (2SK508)
and varactor diodes D2002,D2003,D2005 and D2006,
oscillates between 450 MHz and 480 MHz according to
the programmed transmit frequency. The theory of opera-
tion of the remainder of the PLL circuitry is similar to that
of the RX PLL circuit; however, dividing data from the
Main CPU Q4012 on the CNTL Unit is such that the VCO
frequency is the actual transmit frequency.