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The serial out and alarm/serial
in outputs
are controlled
by the
ACIA
(U118).
R123, R124 and CR105 comprise
a protection
network
for these two outputs,
The serial out output
data is
transmitted
via R124 and pin 6 of the ACIA
(U118).
The
alarm/serial
in data is transmitted/received
via R123 and pin 2
of the ACIA
(U118). The external
trigger
input
and channel
ready output are controlled
by the VIA (U119). R121, R122 and
CR104 comprise
a protection
circuit
for these
two
outputs.
While R126 is a pull up resistor for the external
trigger line. The
external
trigger input is routed
into the circuitry
via R121 and
pin 40 of the VIA (U119). The channel ready output produces
a
TTL level negative
going pulse of greater than 2Mec by way of
R122 and pin 15 of the VIA (U119) when
programmed
to do
SO.
The control
of the relay switching
is accomplished
by serial to
parallel
conversion
involving
shift
registers
U106,
Ulll
and
U127. Also involved
are drivers
(darlington
transistor
arrays)
U105, UllO,
U116 and U126. The serial data is clocked into the
shift registers by the clock line and the data line from the VIA
(U119 pins 18 and 19 respectively).
Once the serial data is
clocked
into the shift registers it does not appear
on the out-
puts of the register until they receive a strobe pulse. The strobe
pulse is generated
by the
BCD to decimal
decoder
U102.
When
the fully loaded
register
receives
the strobe
pulse the
data is outputted
simultaneously
into the respective
drivers
(U126,
U116,
UllO
and
U105).
The
drivers
provide
the
necessary
current
boost while
not altering
the data and then
output
the parallel
data
to the card cage connector
(JIOI I).
The scanner
cards are plugged
into the appropriate
slots in
connector
JlOll,
and the necessary
control
to the relays is
provided
through
that connector.
The time and date are kept internally
by a battery
backed
up
clock that is comprised
of crystal YlOl,
NAND gates U109 A,
B,
C and
D, shift
register
U104,
clock
chip
UIOI
and
associated
circuitry.
The timing
is provided
by the 32.768kHz
crystal YlOl.
4.4 DISPLAY
CIRCUIT
The display
data is outputted
on PA0 through
PA7 from the
VIA (U119) by way of connector
JlOlO.
The data is updated at
a 1 kHz rate which
means each digit is on for lmsec.
Each up-
date begins
by presenting
new segment
information
on the
VIA (I/O) bus (PAO-PA7) and outputting
a clock pulse on CA2.
The clock pulse inputs to U203 and shifts a digit enable bit to
the next digit to be enabled.
Every eight times the display is up-
dated,
a digit enable
bit is generated
at PB3 and is routed
to
the enable data input of the shift register.
The first four digit drivers drive the rows of the switch
matrix.
The switches
are arranged
in a four by six matrix. The segment
drivers
are 0201
through
CQO8. In addition
to driving
the
various
segments,
they also activate
the appropriate
LEDs.
4.5 IEEE-488 INTERFACE
CIRCUITRY
/
The IEEE-488 interface
circuitry
is comprised
of GPIB adapter/
(UlO71,
GPIB
octal
transceiver
(U108)
and
GPIB
octal!
transceiver
WI 14) and associated
capacitors.
The standard)
bus connector
(J1002)
is located
on the
rear panel.
Thr
primary
address
is set from
front
panel program
number
3
There are no primary
address dip switches.
Refer to paragraph,
2.6.4 for complete
details concerning
the primary
address.
GPIB adapter
U107 is the heart of IEEE-488 interface
circuitry.
U107 is capable
of performing
all IEEE-488 talk/listen
pro-
tocols.
The
data
bus consists of DO through
D7. The address
lines that are routed
to the IEEE-488 circuitry
are AO, Al an
A2. The REN, IFC, NDAC,
NRFD, DAV, EOI, ATN and SR:
lines are all controlled
by U107. Before the data is transmitteo
to the IEEE-488 bus via connector
J1002 it is buffered
by the
octal bus transceivers
U108and
U114. The REN, IFC, EOI lines
etc., are buffered
by U114. U108 and U114 operate on the tri-
state output
principle.
That is, the output is either High, Low or
in a high impedance
state.
4-314-4
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