Input And Output Circuits; Video Output; Trigger Input; Hd And Vd Input - JAI CV-A50 Operation Manual

5.3. Input and Output Circuits

In the following schematic diagrams the input and output circuits for video and timing signals
are shown. Jumper settings are shown as for factory default. For alternative connections refer
to "10.1. CV-A50/60 emulating CV-M50 interfacing."

5.3.1. Video output

The video output is a 75 Ω DC coupled
circuit. The BNC connector and pin #4 on
the 12-pin connector is in parallel. Avoid
double termination. The video DC level is
shown with 75 Ω termination.

5.3.2. Trigger input

The trigger input is AC coupled. To allow a
long pulse width, the input circuit is a flip
flop, which is toggled by the negative or
positive differentiated spikes caused by
the falling or rising trigger edges.
The trigger polarity can be changed.
Trigger input level 4 V ±2 V.
The trigger-input impedance is 1 kΩ.
JP1 and JP4 are for alternative
configuration for pin #10.

5.3.3. HD and VD input

The input circuit for external HD and VD
signals are shown. It can be 75 Ω terminated
by closing SW2. SW1 will switch to output the
internal HD and VD signal.
HD and VD input level is 4 V ±2 V.

5.3.4. HD, VD, PCLK, WEN and EEN output

Output circuit for these signals are 75 Ω
complementary emitter followers. It will
deliver a full TTL signal. JP5 and JP3 are for
alternative configuration for pin #10.
Output level ≥4 V from 75Ω. (No
termination).
The WEN polarity can be changed.
CV-A50 / CV-A60
Fig. 4. Video output.
Trigger Trigger
input input
Fig. 5. Trigger input.
Fig. 6. HD and VD input.
TTL TTL
Fig. 7. HD, VD, PCLK, WEN and EEN output.
- 5 -
CXA1310 CXA1310 L L
2µ7 2µ7 75 75
32 32
82p 82p
NC NC
+12v +12v
JP1 JP1
100 100
#11/12 #11/12 JP4 JP4
100n 100n
100n 100n
#5/6 #5/6
NC NC NC NC
GND GND
From VD HD From VD HD
output output
VD HD VD HD
SW1 SW1
Input/output Input/output
1n 1n
1k 1k
NC NC
GND GND
10k 10k
220 220
10 10
10 10
10k 10k
#4/12
#4/12
Video Video
Output Output
BNC BNC
GND GND
+5V +5V
33k 33k
1k 1k
33k 33k
100k 100k
1k 1k
1n 1n
+5V +5V
33k 33k
+ +
1k2 1k2
10µ 10µ
47p 47p
75 75
SW2 SW2
4k7 4k7
+5V +5V
VD, HD VD, HD SW1 SW1
67 67 WEN/ EEN WEN/ EEN
JP2 JP2
PCLK PCLK
WEN WEN
JP5 JP5
JP3 JP3
300 mV 300 mV
420 mV 420 mV
TTL TTL
GND GND
TTL TTL
#6/6 #6/6
#9/12 #9/12
#10/12 #10/12
GND GND