Clock Circuitry; Reset; Low-Voltage Inhibit; Background Debug Mode (Bdm) Interface - Motorola M68EVB912B32 User Manual

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HARDWARE REFERENCE

4.6 CLOCK CIRCUITRY

The EVB comes with a 16-MHz crystal, Y1, with appropriate startup capacitors. The board

should be able to accommodate most crystals and ceramic resonators.

Header W16 may be used to disconnect Y1 from the MCU's on-chip oscillator. An external

clock may then be supplied to EXTAL through W16.

The reset circuit includes a pull-up resistor, reset switch (S1), and a low-voltage inhibit device

with a toggle voltage of 3.0 Vdc. This reset circuit drives the MCU's RESET* pin directly.

Note that header W15 may be used to provide an alternate reset input.

Low voltage inhibition (LVI) uses a Motorola undervoltage sensing device (U1) to automatically

drive the MCU's RESET* pin low when Vdd falls below U1's threshold. This prevents the

accidental corruption of EEPROM data if the power-supply voltage should drop below the

allowable level.

Depending on the date of manufacture, the sensing device installed on the EVB may have either a

2.7-volt or 4.5-volt threshold. U1 may be identified by part number:

MC34164P-3  2.7 Vdc

MC34164P-5  4.5 Vdc

If operation below U1's threshold (but no less than 2.7 Vdc) is required, one of two methods can

be used:

1. Replace U1 with a device that has the required threshold voltage.

2. Cut the trace on header W15 to disconnect U1 from the RESET* line. If this is done,

an external reset signal should be provided via W15 in case the supply voltage falls

below the acceptable level.

The MCU's serial BDM interface can be accessed through two 2x3 headers, BDM IN (W9) and

BDM OUT (W12). The pin assignments are shown in Table 4-3.

4-6

68EVB912B32UM/D

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