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PowerQUICC II Initializations
• LETM = 1:
• NPQM = 111: Non PowerQUICC II master connected
• EXDD = 0:
• ISPS = 0:
The resulting register value is BCR=0xA01C0000.
System Protection Control Register (SYPCR)
This register controls the software watchdog. It can be read at any time but can be written
only once after system reset. During the first phases of a development, it may be simpler to
disable the watchdog by setting SWE to 0 in this register just after reset.
The resulting register value is SYPCR=0xFFFFFFC0.
60x Bus Arbiter Registers (PPC_ACR, PPC_ALRH, and PPC_ALRL)
In the PPC_ACR register, the following fields must be initialized:
• DBGD = 1:
• EARB = 0:
• PRKM = 0110: Bus parked on internal PowerPC core
Registers PPC_ALRH and PPC_ALRL define the priorities of the various bus masters. On
the 60x bus the recommended priority order is as follows (from the highest to the lowest):
• CPM high priority: highest
• CPM middle priority
• CPM low priority
• External Master (the PowerSpan)
• PowerPC core
The resulting registers values are: PPC_ACR = 0x26, PPC_ALRH = 0x01276345, and
PPC_ALRL = 0x89ABCDEF.
SIU Module Configuration Register (SIUMCR)
The SIUMCR register configures various features in the SIU module, among them the
configuration of several multifunction pins. Its fields must be set as follows:
• BBD = 0:
• ESE = 1:
• PBSE = 0:
• CDIS = 0:
• DPPC = 00:
• L2CPC = 10:
• LBPC = 00:
64
Enable Local Extended Transfer Mode
External Master Delay not disabled
Internal Space Port Size = 64 bits
Assert
DBG after
TS (needed if bus is parked on the
–
–
PowerSpan)
Internal Arbiter used
ABB and
DBB enabled
–
–
GBL/
IRQ1 pin used as
–
–
PPBS/PGPL4 used as PGPL4
–
Core is enabled
IRQ/DP pins used as
–
–
L2 cache pins configured as BADDR
Local bus pins used as local bus
GBL
–
IRQ
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