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PowerQUICC II CPM Initialization
• RFSDx = 01: Receive frame sync delay for TDMa. 01 for 1 clock delay.
• DSCx = 0:
• CTRx = 1:
• SLx = 1:
• CEx = 1:
• FEx = 0:
• GMx = 0:
• TFSDx = 01: Transmit frame sync delay for TDMa. 01 for 1 clock delay.
Final Result of SI1AMR register is 0x0171.
TDM Busses in Independent Direct Mode
According to the TDM busses configuration (
SI1AMR, SI1BMR, SI2AMR and SI2BMR registers must be set as follows:
• Reserved = 0: This bit should be cleared.
• SADx = 000: Starting bank address for the RAM of TDMAx. 000 for first bank,
• SADx = 010: Starting bank address for the RAM of TDMBx. 010 for second bank,
• SDMx = 00: SI Diagnostic Mode for TDMx. 00 means normal operation.
• RFSDx = 00: Receive frame sync delay for TDMx. 00 for no clock delay.
• DSCx = 0:
• CTRx = 1:
• SLx = 1:
• CEx = 1:
• FEx = 0:
• GMx = 0:
• TFSDx = 00: Transmit frame sync delay for TDMx. 00 for no clock delay.
Final Result of SI1AMR and SI2AMR registers is 0x0070.
Final Result of SI1BMR and SI2BMR registers is 0x2070.
70
Double speed clock for TDMa. 0 means the channel clock rate is
equal to the data clock.
Common receive and transmit pin clocks for TDMa. 1 means Rx and
Tx clocks are common.
Sync level for TDMa. 1 means sync active level is 0.
Clock edge for TDMa. When DSCx = 1, data sent on the falling edge
and received on the rising edge.
Frame Sync edge for TDMa. 0 for falling edge.
Grant mode for TDMa. 0 for grant mode not used.
first 32 entries.
first 32 entries.
Double speed clock for TDMx. 0 means the channel clock rate is
equal to the data clock.
Common receive and transmit pin clocks for TDMx. 1 means Rx and
Tx clocks are common.
Sync level for TDMx. 1 means sync active level is 0.
Clock edge for TDMx. When DSCx = 0, data sent on rising edge and
received on falling edge.
Frame Sync edge for TDMx. 0 for falling edge.
Grant mode for TDMx. 0 for grant mode not used.
on page
34), the
Interphase Corporation
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