Debug Port J5 - Interphase 4538 Hardware Reference Manual

Pmc t1/e1/j1 communications controller
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No.
Pin Name

Debug Port J5

On the 4538, a 2x8-pin connector can be implemented to provide access to the BDM
(Background Debug Mode) bus: the PowerQUICC II debug bus. Signals on this connector
have 3.3V TTL electrical levels.
4538 Hardware Reference Manual
Table 5-6. PMC Connector P4 (cont)
Pin Type
Description
Chapter 5: Connectors and Front Panel
W
W
W
W
105

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