1. Manuals
  2. Brands
  3. Interphase Manuals
  4. Controller
  5. 4538
  6. Hardware reference manual

Interphase 4538 Hardware Reference Manual

Pmc t1/e1/j1 communications controller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
®
4538 PMC
T1/E1/J1
Communications Controller
Hardware Reference Manual
Document No. UG4538-001
Print Date:

Advertisement

Table of Contents
loading

Related Manuals for Interphase 4538

Summary of Contents for Interphase 4538

  • Page 1 ® 4538 PMC T1/E1/J1 Communications Controller Hardware Reference Manual Document No. UG4538-001 Print Date:...
  • Page 3 Copyright Notice © 2001 by Interphase Corporation. All rights reserved. Printed in the United States of America, 2001. This manual is licensed by Interphase to the user for internal use only and is protected by copyright. The user is authorized to download and print a copy of this manual if the user has purchased one or more of the Interphase products described herein.
  • Page 4 Contact the reseller or distributor if • You need ordering, service or any technical assistance. • You received a damaged, incomplete or incorrect product. Product Purchased Directly from Interphase Corporation Contact Interphase Corporation directly for assistance with this, or any other Interphase Corporation product.
  • Page 5 END-USER LICENSE AGREEMENT FOR INTERPHASE CORPORATION SOFTWARE IMPORTANT NOTICE TO USER–READ CAREFULLY THIS END-USER LICENSE AGREEMENT FOR INTERPHASE CORPORATION SOFTWARE (“AGREEMENT”) IS A LEGAL AGREEMENT BETWEEN YOU (EITHER AN INDIVIDUAL OR SINGLE ENTITY) AND INTERPHASE CORPORATION FOR THE SOFTWARE PRODUCTS ENCLOSED HEREIN WHICH INCLUDES COMPUTER SOFTWARE AND PRINTED MATERIALS (“SOFTWARE”).
  • Page 6 Limitation of Liability: NEITHER INTERPHASE NOR ITS LICENSORS SHALL BE LIABLE FOR ANY GENERAL, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR OTHER DAMAGES ARISING OUT OF THIS AGREEMENT EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Confidentiality: The Software is copyrighted and contains proprietary and confidential trade secret information of Interphase and its vendors.

  • Page 7: Table Of Contents

    CPM TDM Busses Bank of Clocks Baud Rate Generator Ethernet 10/100BaseT TTY Console Serial Port User-Programmable LEDs The PCI Bridge PowerSpan PCI Configuration Registers PowerSpan PCI Registers PowerSpan Processor Bus Registers PowerSpan DMA Registers PowerSpan Miscellaneous Registers 4538 Hardware Reference Manual Contents...
  • Page 8 TDM Bus Configurations General Multiplex Direct Mode Independent Direct Mode Switched Mode Pass-Through Mode CHAPTER 2 4538 Power-Up Initialization Overview PowerSpan Initialization PowerSpan Hardware Configuration Word PowerSpan Register Initialization Through the I²C Serial EEPROM Other PowerSpan Initializations PowerQUICC II Hardware Configuration Word...
  • Page 9 Transmit Pulse Shape Line LED Control The Ethernet Port Initialization The TTY Framer Initialization CHAPTER 4 Accessing the 4538 on the PCI Side PowerSpan Configuration by the PCI Host PCI Configuration Interrupt Pin Configuration PCI-to-Local Window Configuration Controlling the 4538 Hardware and Software Resets Controlling the PCI-to-Local Interrupt Local to PCI Interrupt (–INTA)
  • Page 10 Contents In Situ EPLD Programming Optimizing the PCI Bus Utilization Effective Ordering of the PCI Accesses PCI Deadlock Situations CHAPTER 5 Connectors and Front Panel Connector Placement Front Panel LED Descriptions RJ48 Connectors J1 and J2 Ethernet 10/100 RJ45 Connector J3 TTY Serial Port J4 PMC Connectors PMC Connectors P1 and P2...
  • Page 11 Connectors and Leds on front panel Figure 5-4. TTY connector : 2.5mm stereo jack plug Figure 5-5. 4538 Connectors ...107 Figure 5-6. 8-Port 6435 Rear Transition Module Layout 4538 Hardware Reference Manual List of Figures ...23 Space...26 ...35 ...36 ...37 ...39 ...40...
  • Page 12 List of Figures Interphase Corporation...
  • Page 13 Table 3-8. E1-CRC4 Specific Initialization. Table 3-9. Slave Mode Initialization Table 3-10. Master Mode Initialization Table 5-1. RJ48 Connectors J1 and J2 Table 5-2. Ethernet 10/100 RJ45 Connector 4538 Hardware Reference Manual ...5 ...7 ...10 ...10 ...11 ...11 ...11 ...12 ...13...
  • Page 14 List of Tables Table 5-3. J4 TTY Serial Connector Table 5-4. PMC Connector P1 ... 98 Table 5-5. PMC Connector P2 ... 100 Table 5-6. PMC Connector P4 ... 103 Table 5-7. J5 Debug Port ... 106 Table 5-8. CompactPCI J3 Pin-Out Table 5-9.

  • Page 15: List Of Examples

    List of Examples 4538 Hardware Reference Manual...
  • Page 16 List of Examples Interphase Corporation...

  • Page 17: Using This Guide

    4538 T1/E1/J1 communications controller. The 4538 is delivered with an Interphase Boot Firmware located in the FLASH memory. This firmware initializes and configures the 4538 hardware at each boot. It also includes built-in self tests and a monitor.

  • Page 18: Byte Ordering And Bit Coding Convention

    Byte Ordering and Bit Coding Convention Byte Ordering and Bit Coding Convention The PCI bus uses the Little Endian Byte ordering: byte 0 in a 32-bit word is the Least Significant Byte (LSB) from an arithmetic point of view and is noted D(7:0). The PowerPC architecture uses the Big Endian Byte ordering: byte 0 in a 32-bit word is the Most Significant Byte (MSB) from an arithmetic point of view and is noted D(31:24).

  • Page 19: Text Conventions

    Do you want the new kernel moved into \vmunix?[y] with a backslash at either the beginning of the continued line or at the end of the previous line. 4538 Hardware Reference Manual ¤ Return) at the end of the command line entry is assumed, ¤...

  • Page 20: Checking And Downloading From The Interphase Www/Ftp Site

    Checking and Downloading from the Interphase WWW/FTP Site Checking and Downloading from the Interphase WWW/FTP Site The latest production software drivers, firmware, and documentation (in Adobe Acrobat PDF or text format) for our current products are available on our WWW / FTP site. Interphase recommends our customers visit the web site often to verify that they have the latest version of driver, firmware, or documentation.
  • Page 21 In these cases, you must choose the proper bus and operating system by typing 8. To download one or more files to your local directory, enter 9. To exit the FTP site, enter 4538 Hardware Reference Manual <directory> for the appropriate subdirectories. quit get <filename>...
  • Page 22 Checking and Downloading from the Interphase WWW/FTP Site Interphase Corporation...

  • Page 23: Hardware Description

    The Interphase 4538 PMC E1/T1/J1 Communications Controller is a network interface PCI Mezzanine Card (PMC) equipped with four software-selectable T1/E1/J1 interfaces (two are provided on the front panel). The 4538 board is intended for 2G and 3G wireless networks, Internet access, and Advanced Intelligent Network (AIN) applications.

  • Page 24: 4538 Hardware Structure

    (FCCs). It can be used to store connection tables for ATM, buffer descriptors, or raw data that is transmitted between channels. It is synchronized with the 60x bus and runs at the same frequency. The 4538 does not provide CPM local memories. The Communication Processor Module (CPM) is a super-set of the PowerQUICC II CPM with additional capabilities.

  • Page 25: Powerquicc Ii Resets

    –HRESET and soft reset signal –SRESET. Instead, two of its interrupt pins, –INT2 and –INT3 respectively, configured as an output are used. These interrupt are controlled with doorbell bits (see 4538 Hardware Reference Manual 59). Hardware and Software Resets Through the PowerSpan on page...

  • Page 26: System Clocks

    The PowerQUICC II Once all the resets are de-asserted, the PowerQUICC II boots using its 8-bit FLASH device. The MPC8260 can control the reset of the various communication peripherals through certain CPM I/O ports. When the PowerQUICC II is in reset state, and until it configures these I/O ports as outputs, these reset signals are activated.

  • Page 27: Figure

    Table 1-1 Figure 1-2 indicate the organization of the local space as defined in the current 4538 Boot Firmware code, with the instruction and data BAT blocks and CS banks used. Table 1-1. PCI Local Space Mapping IBAT/...

  • Page 28: Local Space Mapping

    The PowerQUICC II 0x0000 0000 0x03FF FFFF 0x8000 0000 0x83FF FFFF 0x8FFF FFFF 0xC000 0000 0xCFFF FFFF 0xF000 0000 0xFFFF FFFF 0xF002 0000 0xF002 FFFF 0xF008 0000 0xF008 FFFF 0xFF00_0000 0xFF01_FFFF 0xFF80_0000 0xFFBF_FFFF 0xFFFF_FFFF Figure 1-2. Local Space Mapping Interphase Corporation...

  • Page 29: Memory Controllers

    The sophisticated memory controller units included in the PowerQUICC II are used on the 4538 boards to control all the external devices, except the PowerSpan, which is directly a 60x bus-compatible device. These units are a General Purpose Chip-select Machine (GPCM) for SRAM, FLASH, and peripherals control, three User Programmable Machines (UPM), and two SDRAM control machines (one used for Main SDRAM on 4538).

  • Page 30: Communication Processor Module (Cpm) I/O Ports

    The CPM part of the PowerQUICC II provides several communication functions. These functions use multi-mode pins that are grouped in four I/O ports: Port A, B, C, and D. The 4538 communications controller uses these ports as shown in the following tables: CPM Port A Usage...
  • Page 31 Chapter 1: Hardware Description CPM Port C Usage Table 1-7. CPM Port D Usage 4538 Hardware Reference Manual...

  • Page 32: Cpm Tdm Busses

    The PowerQUICC II Table 1-7. CPM Port D Usage (cont) AUTION The I/O ports described as “Unused” in the tables above must be configured as general purpose outputs (the logical level does not matter) in order to avoid their electrical level to float. CPM TDM Busses The CPM in the MPC8260 features two Serial Interfaces, each one featuring four TDM busses, for a total of eight TDM busses (TDMa1 ...

  • Page 33: Bank Of Clocks

    LXT971A line interface unit controls the Ethernet interface to a RJ45 connector J3. The CPM interface to the line interface unit is a MII (Media-Independent Interface) bus. Table 1-12. Ethernet Signals on the CPM Ethernet Signal CPM I/O Port 4538 Hardware Reference Manual Chapter 1: Hardware Description Description...

  • Page 34: Tty Console Serial Port

    The PowerQUICC II Table 1-12. Ethernet Signals on the CPM (cont) Ethernet Signal CPM I/O Port Three Ethernet LEDs, LED3, LED4, and LED5, driven respectively by the LXT971A LED/CFG(1:3) outputs, are provided on the front panel. TTY Console Serial Port The SMC1 part of the CPM is used as a simple asynchronous serial port for connection to a TTY console.

  • Page 35: The Pci Bridge

    PCI host and the local processor. On the PCI side, the PCI base address of this register space is defined by PCI configuration register PCIBAR1 (offset 0x14). On the local side, the local base address has been conventionally fixed to 0xF0020000. 4538 Hardware Reference Manual &38 &38 &38...

  • Page 36: Powerspan Pci Configuration Registers

    The PCI Bridge The PowerSpan internal register set can be split into six different functional groups: • PCI configuration registers (these registers, defined by the PCI specification, can be accessed in the standard PCI configuration space or in the local PowerSpan internal registers space) •...

  • Page 37: Powerspan Pci Registers

    These registers are used to define the parameters of the PCI-to-Local windows. They are mapped in the PCI memory space (base address defined in PCI configuration register 0x14 PCIBAR1) and in the local space for the local processor (base address 0xF0020000). Table 1-16. PowerSpan PCI Registers Offset Register Description 4538 Hardware Reference Manual...

  • Page 38: Powerspan Processor Bus Registers

    The PCI Bridge Table 1-16. PowerSpan PCI Registers (cont) Offset Register PowerSpan Processor Bus Registers These registers are used to define the parameters of the local to PCI windows. They are mapped in the PCI memory space (base address defined in PCI configuration register 0x14 PCIBAR1) and in the local space for the local processor (base address 0xF0020000).

  • Page 39: Powerspan Dma Registers

    PowerSpan. They are mapped in the PCI memory space (base address defined in PCI configuration register 0x14 PCIBAR1) and in the local space for the local processor (base address 0xF0020000). Table 1-18. PowerSpan DMA Registers Offset Register Description 4538 Hardware Reference Manual...

  • Page 40: Powerspan Miscellaneous Registers

    The PCI Bridge PowerSpan Miscellaneous Registers This group of registers includes several configuration registers for the interrupt functions, as well as various runtime registers: mailboxes, doorbells, interrupt control/status, and semaphores. They are mapped in the PCI memory space (base address defined in PCI configuration register 0x14 PCIBAR1) and in the local space for the local processor (base address 0xF0020000).

  • Page 41: Powerspan I²O Registers

    The PowerSpan provides one interrupt pin on the PCI side (–INTA) and six other interrupt pins (–INT0 to –INT5) on the local side. On the 4538, only –INTA and –INT0 are used for true interrupt functions. The five other pins are used as I/O pins to control several signals.

  • Page 42: Pci To Local Interrupt (Atn)

    The PCI Bridge Interrupt pins –INT1 to –INT4 are configured as output ports and conventionally associated with doorbell bits DB3 to DB6 in the PowerSpan. Each doorbell bit, when set, will activate its corresponding interrupt pin (level = 0), and when reset will deactivate it (level =1). Interrupt pin –INT5 is used as an input.

  • Page 43: Local To Pci Interrupt (-Inta)

    P1_TIx_CTL, and preset at power-up by the serial EEPROM. In the 4538 communications controller, only two windows are enabled. They have been set to a relatively small size (2 MB and 512 KB), in order to comply with high availability operating system requirements.
  • Page 44 The PCI Bridge A PowerSpan PCI-to-Local window must have been enabled in the I²C serial EEPROM, in order to allow the CompactPCI host to detect it at system power-on or after the “Hot Swap insertion” of the board and to map it in the PCI space. The corresponding PowerSpan register “PCI Target Image Control Register”...

  • Page 45: Local Space Access From Pci Memory Space

    When the processor is running, the PCI bus can access all the elements connected to the local bus, except the FLASH boot memory. The accessible elements are the main SDRAM memory (the processor’s SDRAM memory controller must be initialized), the processor 4538 Hardware Reference Manual...

  • Page 46: Access To The Flash Eeprom Through Compactpci

    The PCI Bridge dual port RAM, the QuadFALC framers, and the IMA device. (the processor must have its chip selects programmed). The local space mapping is the same as when accessed by the processor (see PCI Local Space Mapping on page It is not possible to have access to the entire FLASH device when the processor is running, because the FLASH device is an 8-bit data bus device connected to the 64-bit-only local bus of the PowerSpan.
  • Page 47 Chapter 1: Hardware Description On the 4538 board, the serial EEPROM content disables the windows. By default, no Local to PCI window is enabled. It is not recommended using these windows for transfers from or to the PCI local space, because this mechanism can result in bad performance, depending on the other PCI devices tied to the PCI bus.

  • Page 48: In-Situ Eplds Programming

    The PCI Bridge Figure 1-5. PCI I/O or Memory Space Access from Local Space In-situ EPLDs Programming Some glue logic is implemented in some EPLDs that can be programmed in-situ through the PCI interface. Interphase Corporation...

  • Page 49: Board Equipment Register

    The first three bytes are common to several Interphase Boards, so many field values are not possible on the 4538. For instance the 4538 does not have Monarch capability, so the Monarch bit will always be set to 0.
  • Page 50 The PCI Bridge Table 1-24. Hardware Configuration Register Field Descriptions Field Description MPC_ID Microprocessor identifier: 0000: MPC8260ZU200, 200/133/66MHz, rev A.1 0001: MPC8260ZU133, 133/133/66MHz, rev A.1 0010: MPC8260ZU200, 200/133/66MHz, rev B.3 0011-1111: Reserved for future processor versions FLASH_SIZE Flash EEPROM size: 00: 1 Mbytes 01: 4 Mbytes 10: 8 Mbytes...

  • Page 51: Vital Product Data (Vpd)

    The boot memory is a 4Mx8 AMD 29LV033 FLASH EEPROM device, placed in the 60x bus byte lane 0. This non-volatile memory device contains the Reset Configuration Word required by the PowerQUICC II during the power-up phase, the 4538 Interphase Boot Firmware Code, and optionally, your own complete operational code. The FLASH memory is always mapped at address 0xFF800000.

  • Page 52: The Quadfalc T1/E1/J1 Framer

    For more information, see The QuadFALC T1/E1/J1 Framer The 4538 Communication Controller includes one QuadFALC device which controls four independent T1/E1/J1 interfaces. For each interface, the QuadFALC includes a framer and an LIU with data and clock recovery, a frame aligner with two frame elastic buffers for receive clock wander and jitter compensation, a signaling controller with a HDLC controller and 64 bytes deep FIFOs, and an 8-bit micro-processor interface.
  • Page 53 LBO, the shape of the transmit pulse must be adjusted through its registers LIM0, LIM2, XPM0, XPM1, and XPM2 in order to comply with FCC 68 or ANSI T1.403. Table 1-27 provides the values in T1 mode for the 4538 hardware (in E1 mode, default values are suitable) Table 1-27. Transmit Pulse Shape Programming...
  • Page 54 XPB_x, XPC_x and XPD_x) and four receive multifunction ports (RPA_x, RPB_x, RPC_x and RPD_x). The tables below indicate how they are used on the 4538 (The RPD port is detailed for each port, since its use differs from one port to another).

  • Page 55: The Ethernet Transceiver

    The LXT971A reset input is controlled by the PowerQUICC II CPM I/O port PC(24) (0=reset). The LXT971A also includes three programmable LED drivers, which are used to control the LEDs on the faceplate. 4538 Hardware Reference Manual Table 1-29. Ethernet LEDs LXT971 Output...

  • Page 56: Tdm Bus Configurations

    TDM Bus Configurations TDM Bus Configurations General The TDM bus general structures are described in and in Figure 1-7 allows three basic configurations that can each have several variants. The configurations are: Direct Mode: The QuadFALC TDM busses are directly tied to the MPC8260. Two variants exist: •...

  • Page 57: Tdm Busses General Structure

    Chapter 1: Hardware Description Figure 1-6. TDM Busses General Structure 4538 Hardware Reference Manual...

  • Page 58: General Clock Structure (Framer 1 & 2)

    TDM Bus Configurations Figure 1-7. General Clock Structure (Framer 1 & 2) '3// '3// Interphase Corporation...

  • Page 59: General Clock Structure (Framer 3 & 4)

    Figure 1-8. General Clock Structure (Framer 3 & 4) 4538 Hardware Reference Manual Chapter 1: Hardware Description '3// '3//...

  • Page 60: Multiplex Direct Mode

    TDM Bus Configurations Multiplex Direct Mode In this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 1. In multiplex direct mode, the four framers have the same rhythm. The QuadFALC system interface is in multiplex mode; the first QuadFALC TDM bus is directly tied to the CPM TDM bus TDMa1.

  • Page 61: Tdm Busses In Multiplex Direct Mode

    TDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must be tristated. Figure 1-9. TDM Busses in Multiplex Direct Mode 4538 Hardware Reference Manual Chapter 1: Hardware Description...

  • Page 62: Clocks In Multiplex Direct Mode (Framer 1 & 2)

    TDM Bus Configurations Figure 1-10. Clocks in Multiplex Direct Mode (Framer 1 & 2) '3// '3// Interphase Corporation...

  • Page 63: Clocks In Multiplex Direct Mode (Framer 3 & 4)

    Figure 1-11. Clocks in Multiplex Direct Mode (Framer 3 & 4) 4538 Hardware Reference Manual Chapter 1: Hardware Description '3// '3//...

  • Page 64: Independent Direct Mode

    TDM Bus Configurations Independent Direct Mode In this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 1. In independent direct mode, each framer can have its own rhythm. Each QuadFALC TDM bus is directly tied to a CPM TDM bus and has its own clock and frame synchronization signal provided by the QuadFALC.
  • Page 65 Chapter 1: Hardware Description Table 1-31. TDM and Synchronization Signals in Independent Direct Mode (cont) 4538 Hardware Reference Manual...
  • Page 66 TDM Bus Configurations Table 1-31. TDM and Synchronization Signals in Independent Direct Mode (cont) OTES RCLK2, RCLK3 and RCLK4 must be configured as inputs (PC5.CRP=0). XPA1, XPA2, XPA3 and XPA4 should be configured as SYPX (They must not be configured as outputs). TDMc1, TDMd1, TDMc2 and TDMd2 signals are not used and should be tristated.

  • Page 67: Tdm Busses In Independent Direct Mode

    Chapter 1: Hardware Description Figure 1-12. TDM Busses in Independent Direct Mode 4538 Hardware Reference Manual...

  • Page 68: Clocks In Independent Direct Mode (Framer 1 & 2)

    TDM Bus Configurations Figure 1-13. Clocks in Independent Direct Mode (Framer 1 & 2) '3// '3// Interphase Corporation...

  • Page 69: Clocks In Independent Direct Mode (Framer 3 & 4)

    Figure 1-14. Clocks in Independent Direct Mode (Framer 3 & 4) 4538 Hardware Reference Manual Chapter 1: Hardware Description '3// '3//...

  • Page 70: Switched Mode

    TDM Bus Configurations Switched Mode In this mode, PA(7) = SWMODE_N = 0 and PA(0) = COMCLK_N = 1. In switched mode, the QuadFALC multiplexed TDM bus is tied to the first TDM bus on P4. The second TDM bus on P4 is tied to the MPC8260. The TDM busses clock and frame synchronization signals are provided by connector P4.

  • Page 71: Tdm Busses In Switched Mode

    TDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must be tristated. Figure 1-15. TDM Busses in Switched Mode 4538 Hardware Reference Manual Chapter 1: Hardware Description...

  • Page 72: Clocks In Switched Mode (Framer 1 & 2)

    TDM Bus Configurations Figure 1-16. Clocks in Switched Mode (Framer 1 & 2) '3// '3// Interphase Corporation...

  • Page 73: Clocks In Switched Mode (Framer 3 & 4)

    Figure 1-17. Clocks in Switched Mode (Framer 3 & 4) 4538 Hardware Reference Manual Chapter 1: Hardware Description '3// '3//...

  • Page 74: Pass-Through Mode

    TDM Bus Configurations Pass-Through Mode In this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 0. Pass through is possible from framer 1 to framer 2 and vice versa and from framer 3 to framer 4 and vice versa. The four framers have the same rhythm (COMCLK_N = 0). In framer 1 to framer 2 pass-through mode, the first framer is tied to the network in LT mode.
  • Page 75 Chapter 1: Hardware Description Table 1-33. TDM and Synchronization Signals in Pass Through Mode (cont) Unused TDM signals must be tristated. 4538 Hardware Reference Manual...

  • Page 76: Tdm Busses In Pass-Through Mode (1->2 & 3->4 Example)

    TDM Bus Configurations Figure 1-18. TDM Busses in Pass-Through Mode (1->2 & 3->4 Example) Interphase Corporation...

  • Page 77: Tdm Busses In Pass-Through Mode (2->1 & 4->3 Example)

    Chapter 1: Hardware Description Figure 1-19. TDM Busses in Pass-Through Mode (2->1 & 4->3 Example) 4538 Hardware Reference Manual...

  • Page 78: Clocks In Pass-Through Mode (Framer 1 & 2)

    TDM Bus Configurations Figure 1-20. Clocks in Pass-Through Mode (Framer 1 & 2) '3// '3// Interphase Corporation...

  • Page 79: Clocks In Pass-Through Mode (Framer 3 & 4)

    Figure 1-21. Clocks in Pass-Through Mode (Framer 3 & 4) 4538 Hardware Reference Manual Chapter 1: Hardware Description '3// '3//...
  • Page 80 TDM Bus Configurations Interphase Corporation...

  • Page 81: 4538 Power-Up Initialization

    • PB_ARB_EN=0: • P1_ARB_EN=0: • P2_ARB_EN=0: • PWRUP_PRI_PCI=0: • P1_R64_EN=0: 4538 Hardware Reference Manual APP/ASM/STARTUP.ASM Disable PowerSpan arbiter for 60x local bus Disable PowerSpan arbiter for PCI 1 bus Disable PowerSpan arbiter for PCI 2 bus (no PCI 2 bus)

  • Page 82: Powerspan Register Initialization Through The I²C Serial Eeprom

    PowerSpan Initialization • PWRUP_BOOT=0: • PWRUP_DEBUG_EN=0:Disable debug mode • PWRUP_BYPASS_EN=0:Disable PLL bypass PowerSpan Register Initialization Through the I²C Serial EEPROM Table 2-1 provides the PowerSpan Register initialization values stored in the Serial EEPROM. Refer to PowerSpan documentation, section EEPROM Loading for detailed mapping between EEPROM addresses and PowerSpan registers.

  • Page 83: Other Powerspan Initializations

    It is necessary to initialize the PowerSpan Interrupt Map registers in a specific way, in order to use the interrupt pins as specified for the 4538. This can be done by the local processor during its boot and/or by the PCI host.

  • Page 84: Powerquicc Ii Hardware Configuration Word

    64-bit reads into its boot memory (the FLASH) with addresses starting at 0 and incremented by 8. The first eight bytes set its Hard Reset Configuration. For the 4538, the PowerQUICC II Hard Reset Configuration is (must be): • EARB = 0: •...

  • Page 85: Powerquicc Ii Initializations

    After a power-up or a reset exception, the PowerQUICC II must initialize itself and adapt its System Interface Unit (SIU) to the 4538 hardware. It must set up its memory controllers and Chip Selects. Then it must also initialize the SDRAM devices, before using them as its system memory.

  • Page 86: System Protection Control Register (Sypcr)

    PowerQUICC II Initializations • LETM = 1: • NPQM = 111: Non PowerQUICC II master connected • EXDD = 0: • ISPS = 0: The resulting register value is BCR=0xA01C0000. System Protection Control Register (SYPCR) This register controls the software watchdog. It can be read at any time but can be written only once after system reset.

  • Page 87: Bus Transfer Error Registers (Tescr1 And L_Tescr1)

    • LPBSE = 0: The resulting register value is SIUMCR=0x4205C000. Bus Transfer Error Registers (TESCR1 and L_TESCR1) Since there is no parity checking on the 4538, data errors must be disabled (field DMD=1 in registers TESCR1 and L_TESCR1). Memory Controllers...

  • Page 88: Gpcm Controller Initialization

    Microprocessor Family: The Programmer’s Reference Guide (ref MPRPPCPRG MMU Initialization The 4538 local memory mapping is organized in such a way that the Block Address Translation (BAT) mechanism can be used rather than the more complicated Segments and Translation Look-aside Buffers (TLB) mechanism.

  • Page 89: Communication Processor Module Initialization

    CPM microcode and start with the known default CPM microcode. 4538 Hardware Reference Manual instruction. sync 8). In the Interphase boot firmware, this is startup.asm Init. Value Comment Chapter 2: 4538 Power-Up Initialization instruction. The setting isync Communication...
  • Page 90 PowerQUICC II Initializations Interphase Corporation...
  • Page 91 T1/E1/J1 framers, some important register programming is detailed. For more details, refer to the 4538 Boot Firmware sources provided with the CD-ROM and referenced (in italics) in this chapter. See also the 4538 Built-In Self Test and Monitor Manual...

  • Page 92: Tdm Busses In Independent Direct Mode

    PowerQUICC II CPM Initialization • RFSDx = 01: Receive frame sync delay for TDMa. 01 for 1 clock delay. • DSCx = 0: • CTRx = 1: • SLx = 1: • CEx = 1: • FEx = 0: • GMx = 0: •...
  • Page 93 • FEx = 1: • GMx = 0: • TFSDx = 01: Transmit frame sync delay for TDM. 01 for 1 clock delay. 4538 Hardware Reference Manual first 32 entries. mode, the TDM transmitter automatically retransmits the TDM received data.
  • Page 94 PC(31) must be configured as CLK1 input, PC(29) as CLK3 input, PC(19) as CLK13 input, and PC(17) as CLK15 input. See Boot Firmware sources: sys\h\4538.h (search CLK1, CLK3, CLK13 and CLK15). Other TDMx signals also have to be configured on the parallel ports.
  • Page 95 TDMa2, TDMbx, TDMcx, and TDMdx are not used. TDMa1 can transport up to 128 MCC channels. This must be configured in the MCCF1 register. 4538 Hardware Reference Manual Chapter 3: Programming the Peripherals C internal BRG. BRGCLK is itself sourced SMC1 is not connected to TSA.
  • Page 96 PowerQUICC II CPM Initialization MCCF1 register initialization: • Group 1 = 00: Group 1 (MCC channels 0-31) is used by TDMa1 • Group 2 = 00: Group 2 (MCC channels 32-63) is used by TDMa1 • Group 3 = 00: Group 3 (MCC channels 64-95) is used by TDMa1 •...

  • Page 97: Tdm Busses General Structure

    Introduction This section details the QuadFALC register initialization, assuming that for non-specified registers, the initialization is the default value (which is generally 0x00). 4538 Boot Firmware sources provides routines to initialize the framers in T1/J1 or E1 mode. Developers should to refer to them.

  • Page 98: Mapping Of Four 2 Mhz Streams Into An 8 Mhz Stream

    T1/E1/J1 Framer Initialization Multiplexed Direct Mode In multiplex direct mode, the four framers have the same rhythm. SWMODE_N = 1 and COMCLK_N = 1. System Interface QuadFALC is connected to the CPM through an 8 MHz stream. This stream is the concatenation of four 2 MHz streams, corresponding to the four T1/E1/J1 lines.
  • Page 99 For T1/J1 applications, the mapping of the receive 24 line time slots over the 32 available on the system interface is configurable with FMR1.CTM bit. In 4538 Boot firmware, the choice is to select ‘Channel translation mode 1’, by setting FRM1.CTM bit to 1: on reception, the 24 line time slots are contiguously mapped before they are interleaved on the system bus.
  • Page 100 T1/E1/J1 Framer Initialization SEC/FSC Configuration The SEC/FSC signal of the QuadFALC is connected to CPM and is used for the TDM frame synchronization clock (8 KHz synchronization pulse generated by one of the four DCO- Rs). It must be configured as an FSC output by setting GPC1.CSFP1 to 1. Bit GPC1.CSFP0 allows selecting the active level (low or high).
  • Page 101 The multiplexed data stream is internally logically ored. Therefore the selection of the active channel phase has to be configured differently for each single channel (1–4). Programming is done with SIC2.SICS2...0 bit as shown in Table 3-2. See Boot Firmware sources: tst\c\qfalc.c - Functions gvQFalcInitT1, gvQFalcInitJ1 and gvQFalcInitE1. 4538 Hardware Reference Manual...
  • Page 102 T1/E1/J1 Framer Initialization RCLK1 Configuration as TDM bus clock 8 KHz synchronization pulse generated by the internal DCO1-R circuit, synchronized to the lines and provided to P4. SEC/FSC Configuration Dejittered clock generated by the internal DCO1-R circuit, synchronized to the lines and provided to P4.
  • Page 103 (low or high). When using the pairing feature, FSC source must match an active channel as for RCLK1: the source is selected with GPC1.FSS1 and GPC1.FSS0 bits. See Boot Firmware sources: TST\C\QFALC.C Function gvQFalcSetPortSyncSrc. 4538 Hardware Reference Manual...
  • Page 104 T1/E1/J1 Framer Initialization Framing and Line Coding Initialization Common Initialization Table 3-4. Common T1/E1/E1-CRC4 Initialization Register Bit T1 Specific Initialization Table 3-5. T1 Specific Initialization Register Bit E1/E1-CRC4 Common Initialization Table 3-6. E1/E1-CRC4 Common Initialization Register Bit Value Comment Value Comment Value Comment Interphase Corporation...
  • Page 105 Register Bit Clock Synchronization Initialization Slave Mode Table 3-9. Slave Mode Initialization Register Bit Value Comment Master Mode Table 3-10. Master Mode Initialization Register Bit 4538 Hardware Reference Manual Value Comment Value Comment Value Comment Chapter 3: Programming the Peripherals...
  • Page 106 The Ethernet Line Interface Unit (LIU) is a INTEL LXT971A. The LIU is connected to FCC3 through a Media Independent Interface (MII). See Boot Firmware: sys\h\4538.h. The LIU internal registers are initialized through MDC and MDIO Management pins. These pins have to be manually manipulated through PC(25) and PC(26) pins. The LIU PHY address is set to 0 (address pins are cabled to 0V).
  • Page 107 Chapter 3: Programming the Peripherals For a simple SMC1 controller example in polling mode: See Boot Firmware: app\c\montty.c 4538 Hardware Reference Manual...
  • Page 108 The TTY Framer Initialization Interphase Corporation...
  • Page 109 The card is identified through its Interphase Vendor ID (0x107E) and its PCI device ID (0x9070). Its PCI configuration is set up by the PCI host at its power-on or by the “high availability” operating system if the 4538 has been hot inserted. Interrupt Pin Configuration...
  • Page 110 Controlling the PCI-to-Local Interrupt For a normal use, the card should be reset by the PCI host (if needed) using only the –SRESET signal. The –HRESET signal is used for special cases, such as FLASH memory re-programming through PCI. run the board from the PCI side. Example 4-1.
  • Page 111 The PowerSpan provides four memory windows from the PCI memory space to the Local memory space. In the 4538 design, the default setting in the PowerSpan serial EEPROM enables two windows. The first one is set with a size of 2 MB and is intended for “operational”...
  • Page 112 Access to the FLASH EEPROM Through PCI When the processor is running, the PCI bus has access to all the elements connected to the local bus, except the FLASH boot memory: the main SDRAM memory (the processor’s SDRAM memory controller must be initialized), the QuadFALC framers, etc. (the processor must have its chip selects programmed).
  • Page 113 Chapter 4: Accessing the 4538 on the PCI Side Example 4-5. FLASH Read and Write Routines (From PCI Side) 4538 Hardware Reference Manual...
  • Page 114 Serial EEPROM Connected to the PowerSpan FLASH EEPROM Programming Algorithms The boot memory is a 4Mx8 AMD 29LV033 FLASH device. To reprogram the AMD FLASH device, special programming algorithms are defined by AMD, which combine reads and writes with special address patterns. The algorithm descriptions can be found at the AMD web site.
  • Page 115 Prefer the bursts. During a burst, the duration of the transfers after the first one can be very efficient and last only one PCI cycle. On the 4538, only the PowerSpan DMAs can generate efficient bursts, because they do transfers to incremental addresses.
  • Page 116 PCI Deadlock Situations Example: The PCI host sets the DMA buffer descriptors into the local memory, and then it runs the DMA (a write into a PowerSpan register). The DMA starts before the effective completion of the buffer descriptors writes into the local 60x memory, so it loads a bad addresses, a bad byte count, etc., and accomplishes the transfer with this bad data.

  • Page 117: Connectors And Front Panel

    5Connectors and Front Panel Connector Placement Figure 5-1. Connectors on the Component Side &38B/(' &38B/(' &38B/(' &38B/(' Figure 5-2. Connectors and LEDs on the Solder Side 4538 Hardware Reference Manual  Ã  Ã  Ã  Ã Ã Ã  Ã  UU`ÃÃÃÃE#...

  • Page 118: Front Panel

    Front Panel Front Panel Figure 5-3. Connectors and Leds on front panel LED Descriptions CPU_LED1: Board user-programmable green LED controlled by PD(15) CPU_LED2: Board user-programmable green LED controlled by PD(14) CPU_LED3: Board user-programmable red LED controlled by PD(18) CPU_LED4: Board user-programmable red LED controlled by PD(17) LED1:Synchronization signal provided by the Framer 1 for Line 0 LED2:Synchronization signal provided by the Framer 2 for Line 1 LED3: LXT971 LED driver 1...

  • Page 119: Ethernet 10/100 Rj45 Connector J3

    Table 5-1. RJ48 Connectors J1 and J2 Ethernet 10/100 RJ45 Connector J3 Table 5-2. Ethernet 10/100 RJ45 Connector 4538 Hardware Reference Manual Signal Signal Chapter 5: Connectors and Front Panel...

  • Page 120: Tty Serial Port J4

    PMC Connectors TTY Serial Port J4 A 2.5mm stereo jack connector provides a connection to an asynchronous serial device such as a TTY console. Signals on this connector have EIA-232-D electrical levels (RS232) for direct connection to a console. Table 5-3. J4 TTY Serial Connector Figure 5-4.
  • Page 121 Chapter 5: Connectors and Front Panel Table 5-4. PMC Connector P1 (cont) Pin Name Pin Type Description 4538 Hardware Reference Manual...
  • Page 122 PMC Connectors Table 5-4. PMC Connector P1 (cont) Pin Name Pin Type Pin Name Pin Type Description Table 5-5. PMC Connector P2 Description Interphase Corporation...
  • Page 123 Chapter 5: Connectors and Front Panel Table 5-5. PMC Connector P2 (cont) Pin Name Pin Type Description 4538 Hardware Reference Manual...
  • Page 124 PMC Connectors Table 5-5. PMC Connector P2 (cont) Pin Name Pin Type Description Interphase Corporation...

  • Page 125: Pmc Connector P4

    The framers 1, 2, 3 and 4 are respectively tied to the lines 0, 1, 2 and 3. Signal levels are classified in the “Very Low Voltage Directory” by IEC 950 safety standard. Table 5-6. PMC Connector P4 Pin Name Pin Type Description 4538 Hardware Reference Manual...
  • Page 126 PMC Connectors Table 5-6. PMC Connector P4 (cont) Pin Name Pin Type Description Interphase Corporation...

  • Page 127: Debug Port J5

    Table 5-6. PMC Connector P4 (cont) Pin Name Debug Port J5 On the 4538, a 2x8-pin connector can be implemented to provide access to the BDM (Background Debug Mode) bus: the PowerQUICC II debug bus. Signals on this connector have 3.3V TTL electrical levels.

  • Page 128: Isp Enable Jumper Jp1

    4538 and its carrier into a CompactPCI chassis. ISP Enable Jumper JP1 The 4538 includes a location for a jumper at JP1. This location is used during production to enable the programming of the card’s EPLD programmable devices “in-situ”. This location should never be used by the normal user.

  • Page 129: Connectors

    Carrier Card Specification CompactPCI Carrier Card Interphase has defined a combination of cards to allow 4538 rear access configurations in CompactPCI chassis. The combination comprises a 4538 "rear access", a CPCI carrier card and an Interphase 6435 Rear Transition Module. The CPCI carrier card must be a Motorola...
  • Page 130 Carrier Card Specification Table 5-8. CompactPCI J3 Pin-Out (cont) ROW A ROW B J3 Columns 15 to 19 are unused. Table 5-9. CompactPCI J5 Pin-Out ROW A J5 Columns 14 to 19 are unused. ROW C ROW D ROW B ROW C ROW D ROW E...
  • Page 131 Custom Carrier Card Customers who want to implement a 4538 "rear access" on configurations other than those described above will need to design their own line interfaces. For these customers, Interphase can provide additional information, such as schematics and a bill of material for these line interfaces.

  • Page 132: Port 6435 Rear Transition Module Layout

    6435 Rear Transition Module 6435 Rear Transition Module Figure 5-6. 8-Port 6435 Rear Transition Module Layout Interphase Corporation...
  • Page 133 Table 5-10. T1/E1/J1 RJ48 Connector ARNING The 6435 RTM panel includes a green (power) LED, which indicates, when on, that removal of the board is NOT permitted. 4538 Hardware Reference Manual Front Panel on page 96). Signal Chapter 5: Connectors and Front Panel...
  • Page 134 6435 Rear Transition Module Interphase Corporation...
  • Page 135 AMechanical Information PMC Card Dimensions 4538 Hardware Reference Manual...
  • Page 136 Carrier Card Dimension Requirements Carrier Card Dimension Requirements Interphase Corporation...
  • Page 137 IEEE Std 802.3, 2000, IEEE Standards for Local and Metropolitan Area Networks: Media Access Control (MAC) Parameters, Physical Layer, Medium Attachment Units, and Repeater for 100 Mb/s Operation, Type 100BASE-T, PCI-SIG Peripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.2 4538 Hardware Reference Manual Bibliography...
  • Page 138 PICMG 2.0 CompactPCI Specification PICMG 2.5 CompactPCI Computer Telephony Specification PICMG 2.1 CompactPCI Hot Swap Specification PowerPC TM Microprocessor Common Hardware Reference Platform: PowerPC Reference Platform (PRP) Specification, Telecommunication Standards ANSI T1.403-1995: Network-to-customer Installation - DS1 Metallic interface ANSI T1.107-1995: Digital Hierarchy - Formats Specifications. ANSI T1.102-1993: Digital Hierarchy - Electrical Interfaces.
  • Page 139 (D2048S); Attachment requirements for terminal equipment interface. ETSI ETS 300 269 Draft Standard T/NA(91)17 - Metropolitan Area Network Physical Layer Convergence Procedure for 2.048 Mbit/s”, April 1994. ETSI ETS 300 011 - Integrated Services Digital Network (ISDN); Primary rate user-network interface Layer 4538 Hardware Reference Manual...
  • Page 140 1 specification and test principles. ETSI ETS 300 166 - Transmission and Multiplexing (TM); Physical and electrical characteristics of hierar- chical digital interfaces for equipment using the 2 048 kbit/s - based plesiochronous or synchronous digital hierarchies. ETSI ETS 300 233 - Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate.
  • Page 141 Infineon PEB22554 / QuadFALC T1/E1/J1 framer Intel LXT971A - 3.3V Dual-Speed Fast Ethernet Transceiver Motorola CompactPCI CPV8540B and MCPN750 carrier boards 4538 Hardware Reference Manual...
  • Page 142 Interphase Corporation...
  • Page 143 Read-Only Memory Chip mounted on the printed circuit board used to provide execut- bootROM able boot instructions to a computer device. 4538 Hardware Reference Manual layer in the form of 48-byte ATM payload segments. and SAR. AALs differ on the basis of the source-destination timing used,...
  • Page 144 Glossary Basic Rate Interface switched communication of voice, video, and data. Board Support Package A board support package consists of documentation and software used to configure and install a specific operating system on a specific product. Broadcast and Unknown Server Multicast server used in ELANs that is used to flood traffic addressed to an unknown destination and to forward multicast and broadcast traffic to the appropriate clients.
  • Page 145 International Organization for Standardization International organization that is responsible for a wide range of standards, including those relevant to networking. ISO developed the popular networking reference model. 4538 Hardware Reference Manual signals. network in which an Ethernet or Token Ring...
  • Page 146 Glossary International Telecommunication Union Telecommunication Standardization Sector Interna- ITU-T tional body that develops worldwide standards for telecommunications technologies. The ITU-T carries out the functions of the former CCITT. Japanese transmission standard Local-Area Network High-speed, low-error data network covering a relatively small geographic area (up to a few thousand meters).
  • Page 147 Synchronous Transport Module level 1 One of a number of STM-1 structure for the 155.52-Mbps lines used to carry 4538 Hardware Reference Manual X.25 “daughter” card designed to mount on a “mother card”. ISDN interface to primary rate access. Primary rate access consists of a sin- Channels for voice or data.
  • Page 148 Glossary Synchronous Transport Signal Synchronous Transport Signal level 1 Basic building block signal of SONET, operating at 51.84 STS1 Mbps. Faster SONET rates are defined as STS-n, where n is a multiple of 51.84 Mbps. Switched Virtual Circuit Virtual circuit that is dynamically established on demand and is torn down when transmission is complete.
  • Page 149 PCI Status PCI Subsystem Device ID PCI Subsystem Vendor ID PMC Connectors Resets Revision Identification Serial EEPROM Structure 4538 Hardware Reference Manual T1 Transmit Pulse Shape programming Transmit Pulse Shape programming types Vendor and Device Identification Vital Product Data Index...

Table of Contents