Powerspan Miscellaneous Registers - Interphase 4538 Hardware Reference Manual

The PCI Bridge

PowerSpan Miscellaneous Registers

This group of registers includes several configuration registers for the interrupt functions,
as well as various runtime registers: mailboxes, doorbells, interrupt control/status, and
semaphores. They are mapped in the PCI memory space (base address defined in PCI
configuration register 0x14 PCIBAR1) and in the local space for the local processor (base
address 0xF0020000).
Offset Register
18
Table 1-19. PowerSpan Miscellaneous Registers
Description
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