Communication Processor Module Initialization; I/O Port Initialization - Interphase 4538 Hardware Reference Manual

The instruction and data caches are enabled through bits ICE and DCE of register HID0
respectively. The setting of ICE bit must be preceded by an
of DCE bit must be preceded by a

Communication Processor Module Initialization

I/O Port Initialization

The CPM I/O ports have to be configured according to their usage (see
Processor Module (CPM) I/O Ports on page
done during the early phase of the boot (in
Each CPM port is set by four registers in the Internal Register Area: PDIRx, PPARx,
PODRx, and PDATx.
Register
CPM RCCR Reset
At boot, it is important to reset the RISC Controller Configuration Register (RCCR) in
order to disable any previously loaded CPM microcode and start with the known default
CPM microcode.
4538 Hardware Reference Manual
Table 2-3. CPM Port Register initialization Values
Address Init. Value
instruction.
sync
8). In the Interphase boot firmware, this is
).
startup.asm
Comment
Chapter 2: 4538 Power-Up Initialization
instruction. The setting
isync
Communication
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