Embedded Pci-X 100 Mhz; Embedded Pci-X 100 Mhz Topology; Embedded Pci-X 100 Mhz Routing Recommendations - Intel 41210 Design Manual

PCI-X Layout Guidelines
8.6.2

Embedded PCI-X 100 MHz

This section lists the embedded routing recommendations for PCI-X 100 MHz.
the block diagram of this topology and
Figure 19. Embedded PCI-X 100 MHz Topology
Table 11.

Embedded PCI-X 100 MHz Routing Recommendations

Parameter
Reference Plane
Board Impedance
Stripline Trace Spacing
Microstrip Trace Spacing
Break Out
Group Spacing
Trace Length 1 (TL1): From
41210 Bridge signal Ball to
first junction
Trace Length: TL_EM1: from
41210 Bridge signal ball to
the first embedded device
Trace Length TL_EM2 -
TL_EM3: from junction to the
embedded device
Length Matching
Requirements:
Number of vias
40
Table 11 describes the routing recommendations.
TL_EM1 EM1
TL1
Routing Guideline for Lower AD Bus
Route over an unbroken ground plane
60 +/- 15%
12 mils from edge to edge
18 mils, from edge to edge
5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils
Spacing from other groups: 25 mils min, edge to edge
0.5" min - 3.0" max
2.5" min - 3.5" max
1.5" min - 3.5" max
Clocks coming form the clock driver must be on the same layer and length
matched to within 25 mils.
4 vias max per path
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Figure 19
TL_EM3 EM3
TL_EM2 EM2
shows
B2720 -01