Embedded Pci-X 133 Mhz; Embedded Pci-X 133 Mhz Topology; Embedded Pci-X 133 Mhz Routing Recommendations - Intel 41210 Design Manual

8.6.1

Embedded PCI-X 133 MHz

This section lists the routing recommendations for PCI-X 133 MHz without a slot.
the block diagram of this topology and
Figure 18. Embedded PCI-X 133 MHz Topology
Table 10.

Embedded PCI-X 133 MHz Routing Recommendations

Parameter
Reference Plane
Board Impedance
Stripline Trace Spacing
Microstrip Trace Spacing
Break Out
Group Spacing
Trace Length 1 (TL1): From
41210 Bridge signal Ball to
first junction
Trace Length 3 junction of
TL_EM1 and TL_EM2 to the
embedded device
Length Matching
Requirements:
Number of vias
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Table 10 describes the routing recommendations.
TL1
Routing Guideline for Lower AD Bus
Route over an unbroken ground plane
60 +/- 15%
12 mils from edge to edge
18 mils, from edge to edge
5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils
Spacing from other groups: 25 mils min, edge to edge
1.75" min - 4.0" max
1.25" min - 3.25" max
Clocks coming form the clock driver must be on the same layer and length
matched to within 25 mils.
3 vias max per path
PCI-X Layout Guidelines
Figure 18
EM1
EM2
shows
B2719 -01
39