Intel g41 express chipset & intel ich7 chipset based m/b for lga 775 quad core ready intel core processor family (16 pages)
Summary of Contents for Intel 41210
Page 1
® Intel 41210 Serial to Parallel PCI Bridge Evaluation Board User’s Guide October 2004 Order Number: 278947-002...
Page 2
® The Intel 41210 Serial to Parallel PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Contents Revision History Date Revision Description -Updated naming terminology in Sections 2.0 and 3.0. -Corrected PCI Bus name Header Connectors J5 and J6 in October 2004 Section 4.0. -Corrected Switch S3 and S4 PCI-X 66 MHZ Pos 3 settings in Table 1.
The Intel® 41210 Serial to Parallel PCI Bridge evaluation board is a PCI-Express enabling tool with PCI-X expansion slots that are used to evaluate the operation of the 41210 Bridge. The 41210 Bridge evaluation board can be used to perform the following functions: •...
Major Components Major Components The major components for the 41210 Bridge include: • For the A Secondary: — J11 is the PCI-X 100/66 MHz card slot. — J7 is the PCI-X 133 MHz card slot. • For the B Secondary: —...
DIP Switches DIP Switches The 41210 Bridge uses a combination of switches and jumpers to control the various configuration options. The following sections describe these controls. Figure 2. Switches, Jumpers, and Connectors Location AUX "B" PCI-X SLOT 2B AUX "A" PCI-X SLOT 2A PCI-X SEC A SLOT 1A ®...
All 0’s CLOSED Note: BOLD settings are Defaults. Jumpers In addition to the DIP switches, the 41210 Bridge provides stake-pin jumpers for selecting special features. The jumpers can be used for debugging and for evaluating special features. Table 3 through Table 8 show the configuration jumpers and the jumper function.
DIP Switches Table 3. Jumper Connections, JTAG Port Jumper Function Default J1-2,1 Not Installed Test Clock J1-4,3 Not Installed Test Data Out J1-6,5 Not Installed Test Data In J1-8,7 Not Installed Test Mode Select TRST# J1-10,9 Not Installed Test Reset J1-1,3,5,7,9 J1-11,12 Table 4.