Pci Clock Distribution And Matching Requirements - Intel 41210 Design Manual

PCI-X Layout Guidelines
Figure 17.

PCI Clock Distribution and Matching Requirements

A_CLKIN
Notes:
– PCI Clock Lengths X0, X1, X2, X3 and X4 should be matched within 0.1 inch of each other.
– Minimum separation between two different CLKs, "d".
– Minimum separation between two segments of the same CLK line, "a".
36
22
®
Intel
A_CLKO0
41210
22
A_CLKO1
Bridge
d
A_CLKO2
22
A_CLKO3
A_CLKO4
A_CLKO6
22
22
22
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
X0
PCI
Device 1
a
PCI
X1
Device 2
PCI
X2
Device 3
PCI
X3
Device 4
PCI
X4
Device 5
B1499-04