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MPC5668EVB Users Manual Rev 0.1
3.3.3 Reset Boot Configuration (J69)
The MPC5668 has a single boot configuration pin (BOOTCFG) which determines the boot location of the
MCU based on the state of the pin at POR (Power On Reset). This is shown in the table below:
Jumper
J69 (BOOT CFG)
3.4 ONCE and Nexus Configuration (J32, J70)
The EVB supports a standard ONCE cable with a 14-pin 0.1" walled header footprint. There is also a 38-pin
MICTOR connector for Nexus debug. Nexus debug is only supported when using a 256MAPBGA MPC5668.
There are two generic jumpers associated with both the ONCE and Nexus, as detailed below
Some debug probes have the ability to assert and also monitor the state of the MCU reset line. This is not
possible when the reset signal is buffered so a jumper (J32) is included to allow routing the debug reset signal
direct to the MCU reset pin or via the EVB Reset-In buffering.
Jumper
Position
1-2 (D)
J32 (JRST)
2-3
Some debug manufacturers specify whether the debug TCLK signal is pulled low or high. Jumper J70
provides the ability to select whether TCLK is pulled to GND or VDDE2.
should be pulled to GND.
Jumper
Position
1-2 (D)
J70
(TCLK PULL)
2-3
Note – J70 is located to the right of the reset LED's, out-with the ONCE / Nexus connector area.
MPC5668EVBUM/D
Table 3-10 BOOTCFG Control
Position
PCB Legend
1-2 (D)
FLASH
2-3
SERIAL
ON
Table 3-11 JTAG / NEXUS Target Reset Routing
PCB Legend
Description
JTAG reset signal is buffered to MCU RESET pin
BUF
(connected to the MCU Reset-In circuitry)
JTAG reset signal is connected direct to MCU
DIR
RESET pin
Table 3-12 ONCE / NEXUS TCLK Termination Control
PCB Legend
Description
JTAG / NEXUS TCLK signal is pulled to VDDE2 via
VDDE2
10K
JTAG / NEXUS TCLK signal is pulled to GND via
GND
10K
Page 13 of 29
Description
MCU boots from internal flash
MCU boots from external serial source
The
ONCE and NEXUS
connectors are located at
the left hand edge of the
EVB
For low power operation, TCLK
May 2009
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