Fujitsu M3097DG Oem Manual page 84

Scanner Interface
A.3.4 RESELECTION phase
RESELECTION is an optional phase that allows a target to reconnect to an initiator for the purpose
of continuing some operation that was previously started by the initiator but was suspended by the
target (i.e., the target disconnected by allowing a BUS FREE phase to occur before the operation
was complete).
1) Upon completing the ARBITRATION phase, the winning SCSI device has both the BSY and
SEL signals asserted and has delayd at least a bus clear delay plus a bus settle delay. The
winning SCSI device becomes a target by asserting the I/O signal.
2) The winning SCSI device shall also set the DATA BUS to a value that is the logical OR of its
SCSI ID bit and the initiator's SCSI ID bit.
3) The target shall wait at least two deskew delays and release the BSY signal.
4) The target shall then wait at least a bus settle delay before looking for a response from the
initiator.
5) The initiator shall determine that it is reselected when the SEL and I/O signals and its SCSI
ID bit are true and the BSY signal is false for at least a bus settle delay. The reselected
initiator may examine the DATA BUS in order to determine the SCSI ID of the reselecting
target. The reselected initiator shall then assert the BSY signal within a selection abort time
of its most recent detection of being reselected; this is required for correct operation of the
time-out procedure. The initiator shall not respond to a RESELECTION phase if bad parity
is detected. Also, the initiator shall not respond to a RESELECTION phase if other than two
SCSI ID bits are on the DATA BUS.
6) After the target detects the BSY signal is true, it shall also assert the BSY signal and wait at
least two deskew delays and then release the SEL signal. The target may then change the I/O
signal and the DATA BUS. After the reselected initiator detects the SEL signal is false, it
shall release the BSY signal. The target shall continue asserting the BSY signal until it
relinguishes the SCSI bus.
bus clear delay
+ bus settle delay
I/O
BSY
SEL
DB
Appendix A-14
RESELECTION phase
deskew
delayx 2
TARG
deskew
delay x 2
INIT
TARG INIT