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NI 5791 Component-Level Intellectual Property
(CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP provides the same IP integration of the user-defined CLIP, but also allows
the CLIP to communicate directly with circuitry external to the FPGA. Adapter module
socketed CLIP allows your IP to communicate directly with both the FPGA VI and the
external adapter module connector interface.
The following figure shows the relationship between an FPGA VI and the CLIP.
Figure 5. Low-Pass Filter (LPF) Bank
3600 MHz LPF
2400 MHz LPF
1600 MHz LPF
1066 MHz LPF
711 MHz LPF
474 MHz LPF
316 MHz LPF
4400 MHz LPF
NI 5791R User Manual and Specifications | © National Instruments | 11
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