TYAN S4992 Manual page 124

Feature
Memory Configuration
Channel interleaving
Enable Clock to All
DIMMs
MemClk Tristate
C3/ATLVID
Memory Hole Remapping
CS Sparing Enable
DCT Unganged Mode
Power Down Enable
Option
Disabled
Address bits 6
Reserved
Address bits 12
Reserved
XOR of Address
bits [20:16,6]
Reserved
XOR of Address
bits [20:16,9]
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Auto
Always
Enabled
Disabled
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Description
Enabled Channel
Interleaving
Enable unused clocks to
DIMMs even memory slots are
not populated.
Enable/Disable MemClk
Stating during C3 and Alt VID
Enable Memory
around Memory Hole
Reserve a spare memory rank
in each mode.
This allows selection of
unganged Dram mode
(64-bit width).
Auto=Ganged mode
Always=Unganged mode
Enable or disable DDR power
down mode.
Memory
Tri-
Remapping