TMC AI5TV User Manual page 33

Chapter 5 BIOS
Fast RAS to CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This field allows you to determine the timing of transition
from Row Address Strobe (RAS) to Column Address Strobe (CAS). By
default, it is set to 3 CPU clocks.
Refresh RAS# Assertion
This field allows you to determine the number of CPU clocks asserted
for the Row Address Strobe is refreshed. By default, it is set to 5
CLKS.
ISA Bus Clock
This field allows you to select the PCI clock type.
Pipeline Cache Timing
This field allows you to select two timings of pipeline caches, Faster
and Fastest.
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
enabled.
Video BIOS Cacheable
When enabled, accesses to the video BIOS addressed at C0000H to
C7FFFH are cached, provided that the cache controller is enabled.
8 Bit I/O Recovery Time
This field allows you to select the recovery time allowed for 8 bit I/O.
By default, this field is set to 1 Clock.
16 Bit I/O Recovery Time
This field allows you to select the recovery time allowed for 16 bit I/O.
By default, this field is set to 1 Clock.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory
from 15MB and up unavailable to the system. Expansion cards can
only access memory up to 16MB. By default, this field is set to
Disabled.
Peer Concurrency
This field allows you to select the number of PCI devices to be
activated at a time. The default value is Enabled.
AI5TV Motherboard User's Manual 31