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TMC AI5TV User Manual: Chipset Features Setup; Dram Timing

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Chapter 5 BIOS

Chipset Features Setup

This Setup menu controls the configuration of the motherboard
chipset.
Auto Configuration

DRAM Timing

DRAM RAS# Precharge Time
DRAM R/W Leadoff Timing
Fast RAS To CAS Delay
DRAM Read Burst (EDO/FP)
DRAM Write Burst Timing
Fast MA to RAS# Delay CLK
Refresh Ras# Assertion
ISA Bus Clock
Pipeline Cache Timing
System BIOS Cacheable
Video BIOS Cacheable
8 Bit I/O Recovery Time
16 Bit I/O Recovery Time
Memory Hole At 15M-16M
Peer Concurrency
Auto Configuration
This field predefined values for DRAM, cache timing according to
CPU type and system clock. When this field is enabled, the predefined
items will become read-only.
DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower
memory.
DRAM RAS# Recharge Time
DRAM must continuously be refreshed or it will loose its data. This
option allows you to determine the number of CPU clocks allocated for
Row Address Strobe to accumulate its charge before DRAM is
refreshed. If refreshed time is not enough, refresh may be incomplete
and data will be lost.
DRAM R/W Leadoff Timing
This field allows you to set the number of CPU clocks before reads and
writes to DRAM. By default, it is set to 7/6 Leadoff timing.
30
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
: Enable
60ns
3
6
3
x222/x333
x3333
1
4CLKS
PCI CLK/4
Faster
Disabled
Disabled
ESC : Quit
1
F1 : Help
1
F5 : Old Values
Disabled
F6 : Load BIOS Defaults
Enabled
F7 : Load Setup Defaults
AI5TV Motherboard User's Manual
á â à ß : Select Item
PU/PD/+/- : Modify
(Shift) F2 : Color

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