Recommended Pcb Layout; Figure 2-12. Pcb Layout (Top View) - Lantronix MatchPort AR Integration Manual

Recommended PCB Layout

The hole pattern and mounting dimensions for the MatchPort AR device server are
shown in the following drawing:
MatchPort AR™ Integration Guide

Figure 2-12. PCB Layout (Top View)

To optimize noise and cross-talk reduction, noise immunity, and impedance
matching on ETX+, ETX-, ERX+, ERX-, follow these guidelines when routing
traces on the target PCB:
−
Route (ETX+, ETX-) pair as close to each other as possible, and far
away from ERX+, ERX- and other signals
−
Route (ERX+, ERX-) pair as close to each other as possible, and far
away from ETX+, ETX- and other signals
−
Set up PCB routing properties on each pair (ETX+, ETX-) and (ERX+,
ERX-) to achieve 100-ohm impedance.
−
For EMI purposes, connect the metal housing (shield) of the RJ45 jack to
Power Ground or Earth Ground and do not allow floating.
If power ground and earth ground are to be separated, add ceramic
capacitors in the range of 1000 pF to 0.1 uF in a stitching pattern
between the two grounds to provide low impedance paths at high
frequencies. The voltage rating on the ceramic capacitors should be
much higher than the required isolation voltage between the two
grounds.
Connect 3.3V and ground on the MatchPort AR directly to 3.3V power and
ground planes of the target board in place of heavy trace routing. This will
minimize noises as well as voltage drops due to the trace.
Make the RESETIN# trace on the target board as short as possible to avoid
reset occurrences when transient voltages such as those caused by ESD are
present.
2:Description and Specifications
19