TDK Genesys User Manual page 87

A. Fault Enable Register (FENA nn, FENA?)
The Fault Enable Register is set to the enable faults SRQs.
Enable
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2 Over Temperature
3 Foldback
4 Over Voltage
5 Shut Off
6 Output Off
7(MSB) Enable
B. Fault Event Register (FEVE?)
The Fault Event will set a bit if a condition occurs and it is enabled. The register is
cleared when FEVE?, CLS or RST commands are received.
Enable
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2 Over Temperature
3 Foldback
4 Over Voltage
5 Shut Off
6 Output Off
7(MSB) Enable
C. Status Enable Register (SENA nn, SENA?)
The Status Enable Register is set by the user to enable SRQs from changes in power
supply status.
BIT Status name
0 (LSB)
Constant Voltage
1
Constant Current
2
No Fault
3
Fault active
4
Auto-Restart enabled
5
Fold enabled
6
Spare
7 (MSB)
Local Mode
Table 8-12: Fault Enable Register
Fault symbol Bit Set condition
SPARE
User command:
AC
"FENA nn" where nn is
OTP
hexadecimal
FOLD
OVP
SO
OFF
ENA
Table 8-13: Fault Event Register
Fault symbol Bit Set condition
SPARE Fault condition occurs
and it is enabled.
AC
The fault can set a bit,
OTP
but when the fault
clears the bit remains
FOLD
set.
OVP
SO
OFF
ENA
Table 8-14: Status Enable Register
Status symbol Bit Set condition
CV
User command:
CC
"SENA nn" is
NFLT
received, where nn is
hexadecimal bits.
FLT
AST
FDE
Spare
LCL
83
83-530-000 Rev J
Bit reset condition
User command: "FENA nn" where
nn is hexadecimal (if nn="00", no
fault SRQs will be generated).
Bit reset condition
Entire Event Register is cleared
when user sends "FEVE?"
command to read the register.
"CLS" and power-up also clear
the Fault Event Register.
Bit reset condition
User command: "SENA nn" is
received, where nn is
hexadecimal bits.
If "nn"=00, no SRQ is sent when
there is a change in Status
Condition Register.
Always zero
Always zero
Always zero
"SENA nn"
"SENA nn"
command
Always zero
Always zero
Always zero
command