Intel Solid-State Drive 320 Series Product Specification page 15

®
Intel Solid-State Drive 320 Series
Table 11. Serial ATA Power Pin Definitions — 2.5-inch Form Factor
1
Pin
2
P1 Not connected
2
P2 Not connected
2
P3 Not connected
3,4
P4 Ground
3
P5 Ground
3
P6 Ground
3,5
P7 V
5
3,5
P8 V
5
3,5
P9 V
5
3
P10 Ground
6
P11 DAS
3, 4
P12 Ground
7
P13 V
12
7
P14 V
12
7
P15 V
12
Notes:
1. All pins are in a single row, with a 1.27 mm (0.050-inch) pitch.
2. Pins P1, P2 and P3 are connected together, although they are not connected internally to the device. The host may put
3.3 V on these pins.
3. The mating sequence is:
• the ground pins P4-P6, P10, P12 and the 5V power pin P7.
• the signal pins and the rest of the 5V power pins P8-P9.
4. Ground connectors P4 and P12 may contact before the other 1st mate pins in both the power and signal connectors to
discharge ESD in a suitably configured backplane connector.
5. Power pins P7, P8, and P9 are internally connected to one another within the device.
6. The host may ground P11 if it is not used for Device Activity Signal (DAS).
7. Pins P13, P14 and P15 are connected together, although they are not connected internally to the device. The host may put
12 V on these pins.
September 2011
Order Number: 325152-002US
Function
(3.3 V Power)
(3.3 V Power)
(3.3 V Power; pre-charge)
5 V Power
5 V Power
5 V Power
Device Activity Signal
12 V Power; not used
12 V Power; not used
12 V Power; not used
Definition
®
Intel Solid-State Drive 320 Series
Mating Order
2nd Mate
1st Mate
1st Mate
1st Mate
1st Mate
2nd Mate
2nd Mate
1st Mate
2nd Mate
1st Mate
1st Mate
2nd Mate
2nd Mate
Product Specification
15