Clock Generator - Clevo D400S Service Manual

Clock Generator

+3VS
L84
FCM2012V121
1 2
C401
C76 C85 C84 C81 C102 C103 C105
0.1UF 10UF/10V 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
+3VS +3VS
R43
R59
D10
10K 10K C
[15,29] CPUSTP#
1SS355
VTT
R62 C C
B B Q19
R45
E Q20 E 2N3904
10K 2N3904
475_1%
L21
1 2 FCM1608K121
+3VS
C90
0.1UF
+3VS
C77 C78
10UF/10V 0.01UF
Clock Buffer (DDR)
+2.5VS
L33
1 2
FCM2012V121
C523
C208 C565 C207
10U(0805)
10U(0805) 0.01UF 0.1UF
+2.5VS
L94
1 2
FCM1608K121
C560
10U(0805)
Frequency
+3VS
Selection
R67 4.7K
FS0
R66 4.7K FS1
R65 4.7K(R) FS2
[6] FWDSDCLKO
R61 4.7K(R) FS3
R60 4.7K(R) FS4
+2.5V
+3VS
C684
0.1UF
R283 R296 +1.8VS
4.7K
4.7K
BSEL0 [3]
BSEL1 [3]
PLEASE PLACE IN COMP SIDE
AND NEAR TOGETHER
FS4 FS3 FS2 FS1 FS0
BSEL1 BSEL0 Function
0
L L
L H
0
H L
H H
Damping Resistors
Main Clock Generator
Place near to the
Clock Outputs
U28
CLOCK GEN (650)
CLK_VCC3
1
VDDREF
CPU-1
11 40 RP44 1
VDDZ CPUCLK0
CPU-2
C104 13 39 2
VDDPCI CPUCLK#0
19
VDDPCI
CPU-3
0.1UF 28 44 RP43 1
VDD48 CPUCLK1
CPU-4
29 43 2
VDDAGP CPUCLK#1
42
VDDCPU
SD-1 R309
48 47
VDDSD SDCLK
AGP-1 R310
12 31
PCI_STOP# AGPCLK0
AGP-2 R311
30
AGPCLK1
5
VSSREF
ZIP-1 R334
8 9
VSSZ ZCLK0
+3VS ZIP-2 R335
18 10
VSSPCI ZCLK1
24
VSSPCI
FS3 R336
25 14
VSS48 PCICLK_F0/FS3
FS4 R337
32 15
VSSAGP PCICLK_F1/FS4
PCI-1 R338
R37 41 16
VSSCPU PCICLK0
PCI-2 R339
46 17
VSSSD PCICLK1
PCI-3 R340
10K 20
PCICLK2
PCI-4 R341
21
PCICLK3
PCI-5 R342
22
PCICLK4
PCI-6
A 45 23
CPU_STOP# PCICLK5 T
FS0 R331
2
REF0/FS0
FS1 R332
33 3
PD#/VTT_PWRGD REF1/FS1
FS2 R333
4
REF2/FS2
R312
USB-1
38 27
IREF 48M
MULTISEL R313
26
24_48M/MULTISEL
36
VDDA
SMBCLK
35
SCLK SMBCLK [7,15,24]
C83 C82 SMBDAT
34
SDATA SMBDAT [7,15,24]
0.1UF 0.01UF
37
VSSA
ICS 952001
CY 28342
Y5
1 2
MULTISEL
C86 14.318MHz
C92 C91
0.1UF
10PF 10PF
U29
CLOCK BUFFER (DDR48)
BUFFERVCC
3 2 RP75 3 2
VDD CLK0
12 1 4 1
VDD CLK#0
C532 C550 C557 23
VDD
4 RP76 4 1
CLK1
0.1UF 0.1UF 0.1UF 5 3 2
CLK#1
13 RP77 2 3
CLK2
14 1 4
CLK#2
BUF_2.5VS 10
AVDD
17 RP62 1 4
CLK3
C549 C556 16 2 3
CLK#3
0.01UF 0.1UF 24 RP61 2 3
CLK4
25 1 4
CLK#4
SMBCLK
7 26 RP60 2 3
SCLK CLK5
27 1 4
CLK#5
SMBDAT
22
SDATA
R384
19 FB_OUT
FB_OUT
FWDSDCLKO
8
CLK_IN
NEAR DDR SODIMM
FB_IN 20 28
FB_IN GND
15
GND
11
GND
9 6 By-Pass Capacitors
T NC GND
18 Place near to the Clock Buffer
T NC
21
T NC
FB_IN
ICS 93722
CY28352
CPU SDRAM ZCLK AGP PCI
0 0 1 1 100M 133M 66M 66M 33M
0 0 0 1 100M 100M 66M 66M 33M
By-Pass Capacitors
Place near to the Clock
Outputs
4 HCLK-CPU HCLK-CPU
HCLK-CPU [3]
3 HCLK-CPU# HCLK-CPU#
HCLK-CPU# [3]
4P2R-33
4 HCLK-650 HCLK-650
HCLK-650 [5]
3 HCLK-650# HCLK-650#
HCLK-650# [5]
4P2R-33
22
SDCLK
SDCLK [6]
SDCLK
22
AGPCLK
AGPCLK [5]
22
GCLK_AGP
T
AGPCLK
22
ZCLK0
ZCLK0 [9]
22
ZCLK1
ZCLK1 [13]
33 PCICLK961
PCICLK961 [13]
33
PCICLK1394 ZCLK0
T
33 PCICLKPCM
PCICLKPCM [19]
33 ZCLK1
PCICLKLAN
PCICLKLAN [25]
33 PCICLKIO
PCICLKIO [22]
33
PCICLKH8
PCICLKH8 [24]
33 PCICLK961
PCLK_80P
PCLK_80P [20]
PCICLK1394
14.381MHZ
33
REFCLK0
REFCLK0 [9]
33 PCICLKPCM
REFCLK1
REFCLK1 [15]
33
CLKAPIC
CLKAPIC [15]
PCICLKLAN
48 MHZ
22 UCLK48M
UCLK48M [16]
SIO48M PCICLKIO
22
SIO48M [22]
PCICLKH8
UCLK48M
0(R)
R44
DDRCLK3
4P2R-0
DDRCLK3[7]
DDRCLK#3
DDRCLK#3[7]
DDRCLK0
4P2R-0
DDRCLK0[7]
DDRCLK#0
DDRCLK#0[7]
DDRCLK2
4P2R-0
DDRCLK2[7]
DDRCLK#2
DDRCLK#2[7]
DDRCLK4
4P2R-0
DDRCLK4[7]
DDRCLK#4
DDRCLK#4[7]
DDRCLK1
4P2R-0
DDRCLK1[7]
DDRCLK#1
DDRCLK#1[7]
DDRCLK5
4P2R-0
DDRCLK5[7]
DDRCLK#5
DDRCLK#5[7]
22 FB_IN
C533 10PF(R)
Clock Generator (71-D4000-D04) B - 5
Schematic Diagrams
49.9_1%
R34
49.9_1%
R33
49.9_1%
R36
49.9_1%
R35
C75 10PF(R)
C74 10PF(R)
C121 10PF(R)
C120 10PF(R)
C119 10PF(R)
C118 10PF(R)
C117 10PF(R)
C116 10PF(R)
Sheet 4 of 35
C115 10PF(R)
C114 10PF(R)
Clock Generator
C73 10PF(R)