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Errata
90.
Memory Aliasing of Pages As Uncacheable Memory Type and Write Back (WB)
May Hang the System
Problem:
When a page is being accessed as either Uncacheable (UC) or Write Combining (WC)
and WB, under certain bus and memory timing conditions, the system may loop in a
continual sequence of UC fetch, implicit writeback, and Request For Ownership (RFO)
retries.
Implication: This erratum has not been observed in any commercially available operating system
or application. The aliasing of memory regions, a condition necessary for this erratum
to occur, is documented as being unsupported in the IA-32 Intel
Software Developer's Manual, Volume 3, section 10.12.4, Programming the PAT.
However, if this erratum occurs the system may hang.
Workaround:
The pages should not be mapped as either UC or WC and WB at the same time.
Status:
For the stepping affected, see the Summary Tables of Changes.
91.
A Timing Marginality in the Instruction Decoder Unit May Cause an Unpredictable
Application Behavior and/or System Hang
Problem:
A timing marginality may exist in the clocking of the instruction decoder unit which
leads to a circuit slowdown in the read path from the Instruction Decode PLA circuit.
This timing marginality may not be visible for some period of time.
Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting
in an unpredictable application behavior and/or system hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the stepping affected, see the Summary Tables of Changes.
92.
Missing Stop Grant Acknowledge Special Bus Cycle May Cause a
System Hang
Problem:
A Stop Grant Acknowledge special bus cycle being deferred by the processor for a
period of time long enough for the chipset to de-assert and then re-assert STPCLK#
signal may cause a system hang. A processor supporting Hyper-Threading
Technology may fail to detect the de-assertion and re-assertion of STPCLK# signal,
and may not issue a Stop Grant Acknowledge special bus cycle in response to the
second STPCLK# assertion.
Implication: When this erratum occurs in an HT Technology enabled system, it may cause a
system hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the stepping affected, see the Summary Tables of Changes.
Specification Update
®
Architecture
63
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