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41.
Possible Machine Check Due to Line-Split Loads with Page-Tables in
Uncacheable (UC) Space
Problem:
The processor issues a speculative load which splits a 64-byte cache line. At the
same time the page miss handling logic completes a page-walk for a different load.
The resulting translation fills the DTLB and evicts the TLB entry to be used by the
line-split load. Since the page tables are located in UC memory, this generates a load
on the system bus for the Page Directory Entry (PDE). Due to an internal boundary
condition, this load blocks any subsequent loads from the completing.
Implication: The timeout counter activates leading to a machine check.
Workaround:
Avoid placing the page directory and the page table in uncacheable memory
space.
Status:
For the steppings affected, see the Summary Tables of Changes.
42.
IA32_MC1_STATUS MSR ADDRESS VALID Bit May Be Set When No
Valid Address Is Available
Problem:
The
processor
IA32_MC1_STATUS MSR if a valid address is available. If a valid address is not
available, the ADDRESS VALID bit in the IA32_MC1_STATUS MSR should not be set.
In instances where an L1 parity error occurs and the address is not available because
the linear to physical address translation is not complete or an internal resource
conflict has occurred, the ADDRESS VALID bit is incorrectly set.
Implication: The ADDRESS VALID bit is set even though the address is not valid.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
43.
EMON Event Counting of x87 Loads May Not Work As Expected
Problem:
If a performance counter is set to count x87 loads and floating point exceptions are
unmasked, the FPU Operand Data Pointer (FDP) may become corrupted.
Implication: When this erratum occurs, the FPU Operand Data Pointer (FDP) may become
corrupted.
Workaround:
This erratum will not occur with floating point exceptions masked. If floating point
exceptions are unmasked, then performance counting of x87 loads should be
disabled.
Status:
For the steppings affected, see the Summary Tables of Changes.
44.
Software Controlled Clock Modulation Using a 12.5% or 25% Duty
Cycle May Cause the Processor to Hang
Problem:
Processor
(IA32_THERM_CONTROL). The On-Demand Clock Modulation Duty Cycle is controlled
by bits 3:1. If these bits are set to a duty cycle of 12.5% or 25%, the processor may
hang while attempting to execute a floating-point instruction. In this failure, the last
46
should
only
log
clock
modulation
may
the
address
for
L1
be
controlled
via
Errata
parity
errors
in
the
a
processor
register
Specification Update
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