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Errata
84.
Simultaneous Cache Line Eviction from L2 and L3 Caches May Result
in the Write Back of Stale Data
Problem:
If a cache line is evicted simultaneously from both the L2 and L3 caches, and the
internal bus queues are full, an older L3 eviction may be allowed to remain in an
internal queue entry. If, in a narrow timing window an external snoop is generated,
the data from the older eviction may be used to respond to the external snoop.
Implication: In the event that this erratum occurs the contents of memory will be incorrect. This
may result in application, operating system or system failure.
Workaround:
BIOS may contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
85.
Bus Locks and SMC Detection May Cause the Processor to Hang
Temporarily
Problem:
The processor may temporarily hang in an HT Technology enabled system if one
logical processor executes a synchronization loop that includes one or more locks and
is waiting for release by the other logical processor. If the releasing logical processor
is executing instructions that are within the detection range of the self -modifying
code (SMC) logic, then the processor may be locked in the synchronization loop until
the arrival of an interrupt or other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application may
temporarily stop making forward progress. Intel has not observed this erratum with
any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
86.
Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint
Is Set on an FP Instruction
Problem:
The default Microcode Floating Point Event Handler routine executes a series of loads
to obtain data about the FP instruction that is causing the FP event. If a data
breakpoint is set on the instruction causing the FP event, the load in the microcode
routine will trigger the data breakpoint resulting in a Debug Exception.
Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP
instruction. Intel has not observed this erratum with any commercially available
software or system.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
61
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